Method for preparing strained silicon nanowire N-channel metal oxide semiconductor field effect transistor (NMOSFET)

Abstract

The invention provides a method for preparing a strained silicon nanowire N-channel metal oxide semiconductor field effect transistor (NMOSFET). The method comprises the following steps of: forming a silicon nanowire field effect transistor region, forming a hollow layer between a top layer silicon and an oxygen buried layer, and preparing a silicon nanowire on the top layer silicon above the hollow layer; depositing an insulating medium layer, and filling the hollow layer below the top layer silicon; grinding the insulating medium layer, so that the thickness of the insulating medium layer above a source and drain gasket is 20-200nm; etching the insulating medium layer of a grid region until exposing the oxygen buried layer; etching a source and drain gasket region and remaining partial top layer silicon at the bottom; generating a carbon silicon layer in the source and drain gasket region, and in situ doping the source and drain region at the same time; and performing a metal silicon alloy technology and a contact hole technology to lead out source, drainage and grid electrodes. By the method, the current driving ability of N-SiNWFET is effectively enlarged; the misplacement or breakage problems which may occur in middle part of the semiconductor nanowire are avoided; and a grid flank wall technology is not needed, and technological processes are simplified.

Description

technical field [0001] The invention belongs to the field of semiconductors, and relates to a preparation method of a silicon nanowire NMOSFET, in particular to a preparation method of a strained silicon nanowire NMOSFET. Background technique [0002] Currently, the introduction of strain engineering in the fabrication of advanced semiconductor devices is very common. In semiconductor devices manufactured by strain engineering, for MOSFETs with a channel direction of <110>, when the channel direction has tensile stress, the current driving capability of the NMOSFET can be effectively increased, and when the channel direction has compressive stress , can effectively increase the current drive capability of the PMOSFET. [0003] In the same way, for the most advanced semiconductor nanowire field effect transistor (Nanowire Field Effect Transistor, NWFET), if strain engineering is introduced in the direction of the nanowire length (ie, the channel direction), the current...

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Problems solved by technology

[0007] Moreover, the strained thin film layer needs to be removed after the gate is prepared. This is actually a stress memory technology (SMT, Stress Memorized Technology). The channel stress of the semiconductor nanowires generated by it can only reach 0.3GPa, which cannot make the N-NWFET Ion larger increase

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