Digital synchronous pulse wireless low-jitter transmission method

Abstract

The invention relates to a digital synchronous pulse wireless low-jitter transmission method in the field of pulse wireless transmission communication, and the method is especially applicable to wireless low-jitter transmission of radar pulse. Pulse shaping is carried out at a transmitting terminal, a PLL (Phase Locked Loop) circuit is adopted for enabling a reference clock to be in phase synchronization with a pulse synchronous clock, and the synchronized reference clock is utilized for performing digital sampling, coding, modulation and other modulation steps on pulse; and a PLL circuit is adopted at a receiving terminal for enabling a reference clock to be in phase synchronization with the reference clock at the transmitting terminal, the synchronized reference clock is utilized for completing pulse demodulation, decoding, recovery and other demodulation steps, and a low-jitter pulse signal is finally output. The digital synchronous pulse wireless low-jitter transmission method can be used for well recovering the pulse at the transmitting terminal and has low requirements on the clocks in the system, and main circuit components are realized by adopting an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) so as to be low in design and debugging difficulty.

Description

technical field [0001] The invention relates to a digital synchronous pulse wireless low-jitter transmission method in the pulse wireless transmission communication field, and is particularly suitable for wireless low-jitter transmission of radar pulses. Background technique [0002] The commonly used pulse digital sampling wireless transmission method can accurately determine the presence or absence of a pulse signal at the receiving end, but the rising edge and falling edge jitter of the received pulse signal is relatively large. To reduce edge jitter, it is necessary to increase the sampling clock frequency, thereby increasing the sampling rate of the pulse. If the requirement for edge jitter is as low as nanoseconds, the required clock frequency is as high as 1GHz or even higher. Under current technical conditions, this is difficult to achieve. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a pulse digitiz...

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Problems solved by technology

Under the current technical conditions, this is difficult to achieve

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