A low-discrete goose single-point-to-multipoint and multi-point-to-single-point transceiver method
A multi-point transceiver and discrete technology, applied in digital transmission systems, electrical components, transmission systems, etc., can solve the problems of poor discreteness of timing control and achieve the effect of communication transmission
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Publication Date
- 2015-07-29
- Estimated Expiration
- Not applicable · inactive patent
Smart Images
Figure 1 Figure 2 Figure 3
Abstract
Description
technical field
[0001] The invention relates to a low-discrete GOOSE single-point-to-multipoint and multi-point-to-single-point transceiver method, which belongs to the technical field of power system substation automation. Background technique
[0002] The GOOSE communication service is generally used between the intermediate layer device and the process layer device in the smart substation, and the communication service is mainly responsible for the transmission of control commands and status information between the two. In order to meet the principle of direct mining and jumping in smart substation technology, the GOOSE message service between the protection device and the process layer device adopts a point-to-point connection mode, so multiple point-to-point Ethernet ports will be added to the process layer device to meet this requirement. In addition, there are high requirements for the discreteness of specific data transmission and reception in the power system. Acco...
Examples
Embodiment Construction
[0032] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.
[0033] Such as Figure 5 As shown, when transmitting between the process layer and the interval layer in the smart substation, there are 8 network interfaces on the interval layer device, and these 8 network interfaces are connected to 8 network chips respectively, and a network interface is provided on the process layer device. The network interface communicates with its corresponding network chip, the I / O port of the FPGA controller is directly connected to the control pin of the network chip, and the communication process between the interval layer and the process layer is controlled by the FPGA. The specific communication process includes the single-point-to-multipoint sending and receiving method of the process layer to the bay layer and the multi-point-to-single-point sending and receiving method of the bay layer to the process layer. ...