Method for preparing TM-SOI (Thick-Membrane Silicon-On-Insulator) silicon chip
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A TM-SOI, silicon wafer technology, applied in the field of thick film TM-SOI silicon wafer preparation, can solve the problems of uneven thickness of SOI top layer silicon film, poor CMP uniformity control ability, etc. The effect of fewer defects and lower roughness
Inactive Publication Date: 2012-11-21
SHENYANG SILICON TECH
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At the same time, the CMP uniformity control ability is poor, which will cause uneven silicon film thickness on the top layer of SOI
[0007] Therefore, using TM-SOI technology and CMP method to prepare a thick-film SOI material with a top-layer silicon film thickness greater than 1 μm, to achieve the effect of completely removing the damaged layer after the slivers, reducing roughness, and good uniformity, there is a big problem. Process issues and technical difficulties
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Embodiment 1
[0065] The original silicon wafer is P-type, the lattice direction is (100), the resistance value is 10-50ohm / cm, and the surface coverage Silicon dioxide (SiO2), polished on one side, 8 pieces of 8" silicon wafers, the dose is 4.0×10 16 / cm 2 , the implantation energy is 200KeV, hydrogen molecular ions (H 2 + )injection. The substrate silicon wafer is P-type, the lattice direction is (100), the resistivity is 0.010-0.020ohm-cm, and the silicon wafer is polished on one side. Two silicon wafers were bonded into a bonded structure by plasma-enhanced bonding at room temperature, placed in a commercially adjustable temperature microwave oven, and annealed at a transition temperature of 200°C for 15 minutes, and then immediately at this temperature After 15 minutes of microwave irradiation at 2.45GHz frequency and 1000W output power, the film with an average thickness of 0.6452 μm was peeled off to form an SOI wafer material.
[0066] Take 6 pieces of SOI wafer materials prep...
Embodiment 2
[0075] Take 3 pieces of SOI wafer material after CMP treatment formed by the TM-SOI technology in Example 1, place them in the reaction chamber of the epitaxial furnace, raise the temperature to 1130 ° C, pass 80 slm of hydrogen, and bake the surface to remove oxidation layer. Heating to 1200° C., introducing 3 slm of HCl for chemical vapor polishing. After 5s, blow air to remove impurities and HCl, then cool down to 1130°C, and feed 3g / min SiHCl under normal pressure 3 , 50sccm B 2 h 6 , for 300s deposition. Finally, stop passing SiHCl 3 , B 2 h 6 , blowing hydrogen to remove SiHCl 3 , B 2 h 6 , cooled to room temperature, blown away the hydrogen, flushed with nitrogen again, and took out the silicon wafer. Table 3 is the test data:
[0076] table 3
[0077]
[0078] From Table 3, it can be seen that the parameters such as TTV and RMS are significantly better than those of the CMP method, and the SOI formed by the CMP method cannot reach the thickness of the top ...
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Abstract
The invention discloses a method for preparing a TM-SOI (Thick-Membrane Silicon-On-Insulator) silicon chip and belongs to the technical field of SOI preparation. The method comprises the following steps: an SOI silicon chip formed through TM-SOI is subjected to coarse grinding, fine grinding and polishing through a chemical-mechanical polishing method, so a damage layer on the surface of the silicon chip is completely removed through grinding, and a thin-membrane SOI silicon chip is formed; a natural oxide layer and impurities on the surface of the thin-membrane SOI silicon chip are removed by adopting HCL chemical etching, and an SOI silicon chip with high quality is obtained; at deposition temperature, silicon deposition chemical raw material and a doping source are introduced into for depositing a required thin membrane; after the silicon deposition chemical raw material and the doping source are removed, a thick-membrane SOI silicon chip is obtained, and the thickness of a silicon membrane in the top layer of the thick-membrane SOI silicon chip is 1-20 microns. With the adoption of the method provided by the invention, the damage layer and the coarse phenomenon on the surface of the top layer silicon of SOI after the TM-SOI process can be removed, meanwhile the preparation of SOI with the thickness of top layer silicon more than 1micron and good uniformity can be realized simply and efficiently.
Description
technical field [0001] The invention relates to a method for preparing SOI (Silicon on Insulator, silicon on insulator), in particular to a method for growing a silicon thin film with low defect density and uniform film thickness on a TM-SOI substrate. Background technique [0002] SOI is a new type of silicon-based semiconductor material with a unique three-layer structure of "Si / insulator / Si". It passes through an insulating buried layer (usually SiO 2 ) realizes the full dielectric isolation of the device and the substrate, has the advantages of small parasitic capacitance, fast operation speed, small leakage, and low power consumption. At the same time, it eliminates the latch-up effect, suppresses the interference of the pulse current of the substrate, and reduces A soft error occurs. Therefore, SOI is widely used. [0003] As a method of manufacturing SOI, TM-SOI is an SOI technology based on the ion implantation stripping method (smart-cut method). "TM-SOI smart cu...
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