Manufacturing method of PMOS (p-channel metal oxide semiconductor) tube

Abstract

The invention discloses a manufacturing method of a PMOS (p-channel metal oxide semiconductor) tube. The method comprises the following steps: forming a first hard mask layer with a bulge structure on the surface of a semiconductor substrate; respectively growing a drain SiGe epitaxial layer and a source SiGe epitaxial layer on the semiconductor substrates on the two sides of the first hard mask layer by an epitaxial growth technology; forming a second hard mask layer on the drain SiGe epitaxial layer and the source SiGe epitaxial layer; removing the first hard mask to expose the semiconductor substrate from the formed opening; growing a new semiconductor substrate on the exposed semiconductor substrate by the epitaxial growth technology; and forming a first side wall layer and a grid structure on the new semiconductor substrate. Through the method disclosed by the invention, the leakage current of the PMOS tube can be reduced.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a method for manufacturing a PMOS tube. Background technique [0002] Figure 1 to Figure 6 It is a process sectional schematic diagram of a method for manufacturing a P-type metal oxide semiconductor (PMOS) tube in the prior art, and the method mainly includes: [0003] Step 101, see figure 1 1. Provide a semiconductor substrate 1001, grow a gate oxide layer 1002 on the surface of the semiconductor substrate 1001, and deposit polysilicon, and then etch the polysilicon and the gate oxide layer 1002 to form a gate structure. [0004] In this step, the gate oxide layer 1002 is first grown; then, a layer of polysilicon can be deposited on the wafer surface through a chemical vapor deposition process, with a thickness of about 500-2000 angstroms; after that, the polysilicon and the gate oxide layer 1002 are etched. etch to form a gate structure, which includes a gate 1003 made of polysi...

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Problems solved by technology

[0021] However, in the prior art, when the semiconductor substrate 1001 is etched in the above step 104, lattice damage will be caused to the semiconductor 1001, wherein, the closer to the trench side surface and the bottom area, the crystal The more serious the lattice damage is, because the temperature of the rapid thermal annealing treatment in the above-mentioned step 106 cannot be too high, therefore, the rapid thermal annealing treatment in the step 106 is also difficult to repair the lattice damage caused to the semiconductor substrate 1001 due to etching, and this This kind of lattice damage will lead to a relatively large leakage current of the fabricated PMOS transistor

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