Under-voltage locking circuit

Abstract

The invention discloses an under-voltage locking circuit and belongs to the field of electronic technology. The under-voltage locking circuit comprises a first resistor (R1), a second resistor (R2), a first NMOS (N-channel metal oxide semiconductor) transistor (M1), a second NMOS transistor (M2), a third NMOS transistor (M3) and a phase inverter (INV1); one end of the R1 and R2 connected in series is connected with supply voltage in a chip, the other end of the R1 and R2 connected in series is connected with the drain electrode of the M1, the series-connection point of the R1 and R2 is connected with the grid electrode of the M1; the source electrode of the M1 is connected with the drain electrodes of the M2 and M3; the grid electrode of the M2 is connected with the drain electrode of the M1 and the input end of the INV1; the grid electrode of the M3 is connected with the output end of the INV1 , and the output end of the INV1 is used as the output end of the under-voltage locking circuit; and the source electrodes of the M2 and M3 are connected with the ground pin of the chip. The under-voltage locking circuit has the advantages that the structure is simple, the power consumption is less, the area of the chip is saved, and the CMOS (complementary metal oxide semiconductor) compatibility is good, and further, the under-voltage locking circuit also has the hysteresis characteristic.

Description

technical field [0001] The invention belongs to the field of electronic technology and relates to integrated circuit design technology, in particular to an undervoltage lockout circuit. Background technique [0002] The purpose of the power management chip is to provide a stable and reliable power supply for the application system. Any unstable power supply may have a serious impact on the application system. Especially during the start-up process of the power management chip, the phenomenon of unstable power supply is most likely to occur. The reason is that during the start-up process of the power management chip, the external power supply charges the capacitor at the input end of the chip through the input end of the chip, so that the power supply of the chip rises steadily. When the chip reaches its turn-on voltage, the chip starts to work. The internal circuit of the power chip or the load draws current from the charging capacitor, which may pull the power supply voltag...

AI Technical Summary

Problems solved by technology

[0003] The existing undervoltage lockout circuit generally compares the sampled chip power supply voltage with the reference voltage through a comparator to determine whether it is undervoltage. The disadvantage of this method is that the reference circuit and comparator circuit need to be implemented, the circuit structure is complex, and the power consumption is large.

In order to simplify the circuit, a variety of structures have been proposed, but most of them use bipolar transistors, which are not compatible with the CMOS process.

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