Printed circuit board (PCB) signal group delay analysis system and method

Abstract

The invention discloses a printed circuit board (PCB) signal group delay analysis system and a PCB signal group delay analysis method. The method comprises the following steps of: measuring S parameters of a data signal line and a clock signal line from the PCB; normalizing a connecting port between the data signal line and the clock signal line by analyzing the S parameters; analyzing an S parameter differential mode of the data signal line and the clock signal line; calculating the first group delay of the data signal line according to the data transmission frequency and S parameter differential mode of the data signal line; calculating the second group delay of the clock signal line according to the clock frequency and S parameter differential mode of the clock signal line; calculating the group delay time difference of the first group delay and the second group delay; and displaying the group delay between the data signal line and the clock signal line on display equipment when the group delay time difference does not meet the design requirements. According to the method, whether the relative length of the data signal line and the clock signal line is equivalent can be estimated, so that an accurate timing sequence relationship of wiring signals in the PCB is kept.

Description

technical field [0001] The invention relates to a signal time delay evaluation system and method, in particular to a signal group delay analysis system and method of a printed circuit board. Background technique [0002] When evaluating the signal time delay of circuit layout, the most concerned feature is whether the relative lengths of the data (DATA) signal line and the frequency (CLOCK) signal line are equivalent, so as to keep the timing relationship of the signal correct. However, in the real circuit layout, the signal time delay is affected by quite a few factors, such as perforation, crosstalk effect, PCB material, stacked board structure, etc., which is not suitable for the rough estimation relationship of the commonly used time delay of about 6mil per second. Make an estimate. [0003] Generally speaking, in order to keep the frequency signal working normally, it is necessary to regulate the length of the DATA signal line and the CLOCK signal line to be equal in l...

AI Technical Summary

Problems solved by technology

However, in the real circuit layout, the signal time delay is affected by many factors, such as perforation, crosstalk effect, PCB material, stacked board structure, etc., which is not suitable for the rough estimation relationship of the commonly used time delay of about 6mil per second. make an estimate

[0003] Generally speaking, in order to keep the frequency signal working normally, it is necessary to regulate the length of the DATA signal line and the CLOCK signal line to be equal in length when winding the PCB board, but it is impossible to do so in practice.

Therefore, the general design often stipulates that the relative length of the DATA signal line and the CLOCK signal line must be within a certain range, otherwise it is easy to cause frequency problems and cause the system to fail.

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