Integration method for replacement gate of semiconductor device

Abstract

The invention discloses an integration method for a replacement gate of a semiconductor device. The integration method for the replacement gate of the semiconductor device includes: providing a semiconductor substrate; forming a trap area on the semiconductor substrate, and defining an N-type device area and / or a P-type device area; forming sacrifice gate stacks, including a sacrifice gate medium layer and a sacrifice gate electrode layer, on the N-type device area and / or the P-type device area respectively; forming a side wall around the sacrifice gate stacks; forming source / drain areas embedded in the semiconductor substrate on two sides of the sacrifice gate stacks; forming a SiO2 layer on the semiconductor substrate; spin-coating SOG (spin-on glass) to the SiO2 layer, etching the SOG to expose the SiO2 layer; performing differential rate etching to the SOG and the SiO2 layer, and flattening the surface of the SiO2 layer; and forming an N-type replacement gate stack on the N-type device area, and / or forming a P-type replacement gate stack on the P-type device area respectively, wherein the sacrifice gate medium layer is located on the semiconductor substrate and the sacrifice gate electrode layer is located on the sacrifice gate medium layer.

Description

technical field [0001] The present invention relates to the technical field of ultra-deep submicron semiconductor devices, in particular to a method for gate replacement integration of high-k gate dielectric / metal gate semiconductor devices. The method uses sacrificial SiO 2 / Polysilicon gate is used as a sacrificial gate stack. After the planarization process, the sacrificial gate stacks in the N-type device region and the P-type device region are respectively removed to form a high-k gate dielectric / metal gate replacement gate stack to realize N-type and P-type high-k Integration of gate dielectric / metal gate semiconductor devices. Background technique [0002] For more than 40 years, integrated circuit technology has continued to develop according to Moore's law, with continuous shrinking of feature size, continuous improvement of integration, and increasingly powerful functions. Currently, the feature size of metal-oxide-semiconductor field-effect transistors (MOSFETs) ...

AI Technical Summary

Problems solved by technology

However, this method has some insurmountable shortcomings: firstly, the metal gate electrode is easily penetrated by ions implanted into the source / drain, which affects the electrical characteristics of the device; The work function of most metal gate materials will move to the center of the forbidden band after high temperature annealing treatment, resulting in the degradation of device performance

However, this gate-last process also has certain shortcomings, mainly because it is easy to cause damage to the underlying high-k gate dielectric when removing the dummy gate electrode, reducing the reliability of the high-k gate dielectric

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