Method for forming shallow trench isolation (STI) structure

An isolation structure and shallow trench technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as semiconductor devices not working properly, pad oxide layer corrosion is incomplete, etc., to enhance reproducibility and stabilize STI high-level effect

Inactive Publication Date: 2011-05-11
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
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  • Claims
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Problems solved by technology

In this case, there will be incomplete corrosion of the pad oxid

Method used

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  • Method for forming shallow trench isolation (STI) structure
  • Method for forming shallow trench isolation (STI) structure
  • Method for forming shallow trench isolation (STI) structure

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Embodiment Construction

[0028] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0029] In the method for forming a shallow trench isolation structure provided by the present invention, firstly, a pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate; and the pad oxide layer, the silicon nitride layer, and the semiconductor substrate are patterned to form a trench groove; then form a liner oxide on the inner surface of the trench; deposit an insulating medium to form a trench oxide; then planarize the insulating medium; measure the remaining thickness of the silicon nitride layer after planarization, according to the measured The remaining thickness of the trench oxide is etched; finally, the silicon nitride layer and the pad oxide layer are removed to form a shallow trench isolation structure. This method measures the remaining thickness of the silicon nitride layer after the planarization p...

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Abstract

The invention discloses a method for forming a shallow trench isolation (STI) structure. The method comprises the following steps: forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; patterning the pad oxide layer, the silicon nitride layer and the semiconductor substrate so as to form a trench; forming a lining oxide on the inner surface of the trench; depositing an insulating medium so as to form a trench oxide; then carrying out planarization treatment on the insulating medium; measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization, and corroding the trench oxide according to the measured residual thickness; and finally, removing the silicon nitride layer and the pad oxide layer so as to form the STI structure. The method provided by the invention has the advantages that through measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization and selecting the thickness of removed trench oxide according to the residual thickness of the silicon nitride layer, the influence of the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization on the STI height is avoided, the STI height between each batch of wafers is stabilized, and the reproducibility of an STI process is enhanced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a shallow trench isolation structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, integrated circuit manufacturing technology has entered the deep submicron era. The size of semiconductor devices and the isolation structures that isolate semiconductor devices have also shrunk accordingly. At process nodes below 0.13 μm, the isolation between active areas of semiconductor devices is formed by a shallow trench isolation process (STI, Shallow Trench Insulate). [0003] In the prior art, the method for forming a shallow trench isolation structure in a semiconductor substrate first forms a pad oxide layer (pad oxide) and a silicon nitride layer on the surface of the substrate, and then forms the silicon nitride layer, the pad oxide layer, and the semiconductor The substrate is patterned ...

Claims

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Application Information

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IPC IPC(8): H01L21/762H01L21/311
Inventor 元琳尹晶磊
Owner SEMICON MFG INT (SHANGHAI) CORP
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