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Photosemiconductor element and method for manufacturing photosemiconductor element

A technology for optical semiconductor components and manufacturing methods, which can be applied in the directions of semiconductor devices, electrical components, and electric solid-state devices, and can solve problems such as the restriction of conductive pillars.

Active Publication Date: 2013-01-02
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in this technique, although it is possible to absorb the level difference on the surface of the semiconductor substrate, the conductive support (connection electrode) is restricted in order to absorb the level difference on the surface of the semiconductor substrate.

Method used

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  • Photosemiconductor element and method for manufacturing photosemiconductor element
  • Photosemiconductor element and method for manufacturing photosemiconductor element
  • Photosemiconductor element and method for manufacturing photosemiconductor element

Examples

Experimental program
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Embodiment approach 1

[0065] (Structure of Optical Semiconductor Element 10)

[0066] refer to figure 1 An optical semiconductor element 10 according to one embodiment of the present invention will be described.

[0067] figure 1 A schematic diagram showing the structure of the optical semiconductor element 10 according to one embodiment of the present invention is shown in . In the optical semiconductor element 10 , a first conductivity type semiconductor layer 12 is formed on an insulating transparent substrate 11 . Furthermore, the second conductivity type semiconductor layer 13 is formed on a part of the upper surface of the first conductivity type semiconductor layer 12 . In this embodiment, a sapphire substrate 11 is used as the insulating transparent substrate 11 . In this embodiment, the first conductive type semiconductor layer 12 and the second conductive type semiconductor layer 13 are composed of n-type and p-type gallium nitride-based compound semiconductors. Therefore, the first ...

Embodiment 1

[0139] Figure 4 The measurement result of the pulse period dependence of a plating ratio ratio in the manufacturing method of the optical-semiconductor element which concerns on one Embodiment of this invention is shown. The manufacturing method of the optical semiconductor element 10 is based on figure 2 The manufacturing method shown. after passing figure 2 After the steps (a) to (d), bump formation by electroplating was performed (see figure 2 (e)). exist Figure 4 When the bump is formed, the pulse frequency of the electroplating current as the pulse waveform is changed within the range of 0.1 second to 1000 seconds, and the ratio of the thickness of the n-pole bump 52 to the thickness of the p-pole bump 51 is set is the plating ratio.

[0140] exist Figure 4 The measured values ​​are represented by empty circles. The dotted line is a curve obtained as a result of fitting to the measured values. The solid line represents the plating ratio obtained by direct c...

Embodiment 2

[0144] Figure 6 In the manufacturing method of the optical-semiconductor element 10 which concerns on one Embodiment of this invention, the experiment result which measured the relationship of the area ratio of the opening part 21 and a plating rate ratio is shown. The plating conditions in this example are as follows.

[0145] ·Electroplating solution: cyanide-free gold plating solution manufactured by EEJA

[0146] ·Electroplating tank temperature: 52°C

[0147] ·Plating current density: DC 6mA / cm 2

[0148] Object to be plated: Wafer (6 inches) for producing optical semiconductor elements

[0149] Under the above-mentioned conditions, electroplating was performed using a wafer without openings 21 (opening ratio 0%) and a wafer with openings 21 formed (opening ratio 6%). As a result, such as Figure 6 As shown, the following results were obtained: the plating rate ratio was about 1.00 when the area ratio of the opening 21 was 0% (opening ratio 0%), and the plating rat...

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Abstract

The invention provides a photosemiconductor element and a method for manufacturing the photosemiconductor element. The photosemiconductor element (10) comprises a first semiconductor layer (12) formed by a semiconductor of the first conductivity type; a second semiconductor layer (13) formed by a semiconductor of the second conductivity type and formed on a portion of an upper surface of the first semiconductor layer; a first electrode (14a) formed on the other portion of the upper surface of the first semiconductor layer; a second electrode (14b) which is formed on an upper surface of the second semiconductor layer and has an upper surface higher than the upper surface of the first electrode; a first connection electrode (52) formed on the upper surface of the first electrode; a second connection electrode (51) formed on the upper surface of the second electrode; and a protective film (15) which is an insulating protective film covering the upper surfaces of the first semiconductor layer and the second semiconductor layer and has an opening part (21) exposing a portion of the upper surface of the first semiconductor layer.

Description

technical field [0001] This invention relates to the manufacturing method of the optical semiconductor element which has the connection electrode suitable for flip chip (flip chip) mounting, and an optical semiconductor element. Background technique [0002] Light-emitting diodes (LEDs) are widely and commonly used against the backdrop of technical developments such as the realization of whitening and the rapid increase in luminous efficiency. Examples include lighting for general household use, headlights for automobiles, and the like. [0003] From the viewpoint of luminous efficiency, manufacturing efficiency, manufacturing cost, and the like, the structure of LEDs currently in the mainstream is as follows. On an insulating transparent substrate (sapphire substrate, etc.), n-type and p-type gallium nitride-based compound semiconductors are stacked. Then, a portion of the p-type layer is etched to form a state in which the surface of the n-type layer and the p-type layer...

Claims

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Application Information

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IPC IPC(8): H01L33/36H01L33/62H01L33/00
CPCH01L2224/11
Inventor 泽井敬一吾乡富士夫渡边裕二川上克二
Owner SHARP KK