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Semiconductor device, fabrication method for a semiconductor device and electronic apparatus

A device manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of not considering the bonding between substrates and the difficulty of ensuring bonding strength, and achieve the prevention of diffusion, Effects of enhancing reliability and securing bonding strength

Active Publication Date: 2013-01-09
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this buried wiring technique does not take into consideration the bonding between substrates, and the barrier metal layer is placed in a state where the barrier metal layer is exposed from the planarized surface obtained by grinding together with the electrodes and the insulating film.
Therefore, it is difficult to ensure sufficient bonding strength over the entire area of ​​the planarized surface

Method used

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  • Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
  • Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
  • Semiconductor device, fabrication method for a semiconductor device and electronic apparatus

Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach

[0065] 1. Example of the general configuration of the semiconductor device of the first embodiment

[0066] figure 1 A general configuration of a solid-state imaging device, which is an example of a semiconductor device to which the three-dimensional structure of the present invention is applied, is shown. refer to figure 1 , the semiconductor device 1 shown is a semiconductor device with a three-dimensional structure (ie, a solid-state camera), which includes a sensor substrate 2 as a first substrate and a circuit substrate 7 as a second substrate, and the circuit substrate 7 is bonded to the sensor in a stacked state. Substrate 2. In the following description, the sensor substrate 2 as the first substrate is simply referred to as the sensor substrate 2 , and the circuit substrate 7 as the second substrate is simply referred to as the circuit substrate 7 .

[0067]On one surface side of the sensor substrate 2 is provided a pixel region 4 in which a plurality of pixels 3 ea...

no. 2 approach

[0194] 1. Configuration of the semiconductor device of the second embodiment

[0195] Figure 8 A partial cross-sectional configuration of a semiconductor device according to a second embodiment of the present invention is shown. In the following, reference will be made to Figure 8 The detailed configuration of the semiconductor device of the present embodiment will be explained.

[0196] Figure 8The shown semiconductor device 301 is a solid-state imaging device with a three-dimensional structure. In the solid-state imaging device with a three-dimensional structure, the first substrate 302 and the second substrate 307 are bonded to each other such that the bonding surface 341 of the first substrate 302 is bonded to the second substrate. Bonding surfaces 371 of 307 are provided in a facing relationship with each other sandwiching insulating film 312 . In the present embodiment, the semiconductor device 301 is characterized by a structure in which the first substrate 302 a...

no. 3 approach

[0287] 1. The first embodiment

[0288] Problems of Cu-Cu bonding technology in the related art

[0289] Before explaining the semiconductor device according to the first example of the third embodiment of the present invention, refer to Figure 12A , Figure 12B and Figure 13 To illustrate the problems that may occur in the Cu-Cu bonding technology in the related art. Figure 12A shows the general configuration of the two semiconductor components before they are bonded together, and Figure 12B A general cross-section of two semiconductor components after bonding near the bonding interface is shown. also, Figure 13 A problem that may arise in a case where bonding misalignment occurs when bonding two semiconductor members is exemplified.

[0290] exist Figure 12A , Figure 12B and Figure 13 In, the following examples are shown: Among them, including the first SiO 2 layer 611, the first Cu electrode 612 and the first Cu barrier layer 613 of the first semiconductor...

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PUM

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Abstract

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

Description

technical field [0001] The present invention relates to a semiconductor device in which a plurality of substrates are bonded to each other to achieve bonding between electrodes or wirings, a method for manufacturing the semiconductor device, and an electronic device including the semiconductor device. Background technique [0002] A technique for bonding two wafers or substrates to each other so that bonding electrodes formed on the respective semiconductor substrates are bonded to each other has been developed and disclosed, for example, in Japanese Patent Laid-Open Publication No. 2000-299379. [0003] Furthermore, as one of structures for realizing higher integration of semiconductor devices, a three-dimensional structure in which two substrates on which elements and wirings are formed are laminated and bonded to each other has been proposed. When it is desired to manufacture a semiconductor device with such a three-dimensional structure as described above, first, two sub...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/40H01L23/522H01L21/28H01L21/768H01L27/146
CPCH01L2224/80091H01L27/14636H01L2224/05686H01L2224/08145H01L2224/80896H01L2224/05027H01L2224/08121H01L2224/05647H01L2224/05571H01L2224/80895H01L24/05H01L2224/80203H01L21/76843H01L21/7684H01L2224/05578H01L21/76807H01L2224/05546H01L27/14645H01L27/1469H01L2224/80357H01L2224/80011H01L25/0657H01L24/03H01L2224/0903H01L2224/80013H01L2224/80097H01L27/0688H01L24/08H01L24/80H01L2224/05573H01L27/1464H01L23/481H01L23/564H01L2224/05547H01L2924/13091H01L2924/00014H01L2924/12043H01L23/5283H01L2221/1031H01L2224/0508H01L2224/05124H01L2224/05147H01L2224/05166H01L2224/05181H01L2224/80035H01L2224/80935H01L23/53238H01L27/14609H01L27/14621H01L27/14625H01L2224/8034H01L2224/08058H01L2224/09517H01L2224/80345H01L2224/08501H01L27/14627H01L2224/80986H01L2224/80359H01L2224/05569H04N25/70H01L2924/00012H01L2924/05442H01L2924/05042H01L2924/053H01L2924/049H01L2924/00H01L2224/05552H01L24/06H01L24/83H01L2224/02245H01L2224/83345H01L21/76841H01L23/528H01L23/53223H01L23/53266H01L23/53295
Inventor 香川恵永青柳健一萩本贤哉藤井宣年
Owner SONY CORP