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Selective patterning for low cost through vias

A patterning, silicon carbide technology, applied in the field of manufacturing integrated circuits, can solve problems such as device failure, short circuit of metal lines 104, etc.

Inactive Publication Date: 2013-01-16
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Via metal 108 contacts multiple metal lines 104 causing shorting of metal lines 104 and failure of the fabricated device

Method used

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  • Selective patterning for low cost through vias
  • Selective patterning for low cost through vias
  • Selective patterning for low cost through vias

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Embodiment Construction

[0017] An exemplary process is presented for fabricating vias in a substrate using isotropic etching. Shorting of the metal lines on the substrate after isotropic etching is prevented by patterning the barrier layer on the substrate before depositing the metal lines on the substrate. The patterned barrier layer inhibits the openings formed for the vias from exposing more than a single metal line. Therefore, each via only contacts a single metal line. The exemplary process for making vias improves the reliability of manufactured devices and increases the yield of the manufacturing process. The exemplary process also reduces the cost of fabricated devices by using isotropic etching and low cost substrate materials such as glass.

[0018] figure 2 is a flowchart illustrating an exemplary manufacturing process for vias according to one embodiment. The exemplary process begins at block 205 with patterning a barrier layer. Figure 3A is a cross-sectional view illustrating a su...

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Abstract

A block layer (304) deposited on a substrate (302) before deposition of metal lines (308) and etching of a through via (306) enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate (302) may be used to fabricate through glass vias (306) without undercut from the wet etching shorting metal lines (308) on the glass substrate (302). The block layer (304) prevents contact between a conductive layer (310) lining the through via (306) with more than one metal line (308) on the substrate (302). The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias.

Description

technical field [0001] The present invention generally relates to integrated circuits. More specifically, the invention relates to the manufacture of integrated circuits. Background technique [0002] Silicon substrates used in semiconductor devices have a high cost compared to other materials. For example, building passive devices on glass substrates will result in lower cost components. Devices stacked on a substrate, such as a glass substrate, utilize vias to communicate with other components. One potential application for glass substrates and vias is liquid crystal displays. Anisotropic or isotropic etching is used to create vias in the substrate. [0003] Anisotropic etching occurs at different rates along different directions and produces generally straight sidewalls through the substrate. Anisotropic etching includes plasma etching, laser drilling and mechanical drilling. Anisotropic etching is a slow process that reduces the throughput of the manufacturing proc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H05K3/00H01L21/768H01L21/48
CPCH01L21/486H05K3/386H01L21/76898H01L23/15H01L23/49827H05K1/0306H05K3/002H05K2201/0394H01L2924/0002H01L2924/00H05K3/00H01L21/768H01L21/48
Inventor 李易明马里奥·弗朗西斯科·韦莱兹顾时群
Owner QUALCOMM INC
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