Parallel testing method
A technology of parallel testing and testing machines, which is applied in the direction of electronic circuit testing, etc., and can solve problems such as inability to measure a single chip, damage to the chip to be tested, and difficulty in distinguishing
Inactive Publication Date: 2013-01-23
CHINGIS TECH CORP
View PDF5 Cites 5 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
However, with this design method, when one of the chips under test is short-circuited, the impact of a large current will damage the chip under test that shares the power supply with it.
Furthermore, in some test procedures of the power pins of the chips to be tested, it is also impossible to measure a single chip due to the relationship of power sharing, and it is difficult to distinguish what caused the abnormal situation.
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0020] Please refer to figure 1 . figure 1 It is a flowchart of a parallel testing method in an embodiment of the present invention. Please also refer to figure 2 . figure 2 It is a schematic diagram of the connection between the test machine 20 and several chips 22 to be tested in one embodiment of the present invention. The parallel testing method includes the following steps (it should be understood that the steps mentioned in this embodiment, unless the order is specifically stated, can be adjusted according to actual needs, and can even be executed simultaneously or partially simultaneously).
[0021] In step 101, provide as figure 2 The test machine 20 and several chips 22 to be tested are shown. The chip 22 to be tested is a finished product after wafer slicing, grinding, exposure, development, implantation, etching and other processes are completed. However, the chip 22 to be tested still needs to undergo some tests to ensure its normal operation and complete ...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention provides a parallel testing method, which comprises the following steps that: a testing machine is provided, wherein the testing machine contains a driving channel and a power channel, and the driving channel contains a first group and a second group; a plurality of chips to be tested are provided, wherein each chip to be tested contains a plurality of signal pins and at least a power pin; the signal pins of each chip to be tested are connected to the driving channel located at the first group; the power pins of each chip to be tested are respectively parallelly connected to the driving channel located at the second group; and the signal pins of each chip to be tested receives driving signals from the connected driving channel located at the first group, and the power pins of each chip to be tested respectively receive power signals with mutually exclusive sources from the parallelly connected driving channel located at the second group so as to carry out parallel testing on the chips to be tested.
Description
technical field [0001] The present invention relates to an electronic device testing method, and in particular to a parallel testing method. Background technique [0002] Circuit probing is the last step in the chip manufacturing process. However, it often takes a lot of time to test a large number of chips. If a single machine can test many chips at the same time, it will save a lot of testing costs and time costs. In order to achieve parallel testing, in the past, several chips to be tested usually share the power provided by one testing machine, so as to achieve the purpose of parallel testing under the condition that the testing machine has not many power supply channels. However, with such a design method, when one of the chips under test is short-circuited, the impact of a large current will damage the chip under test that shares the power supply with it. Furthermore, in some test procedures of the power pins of the chips to be tested, it is also impossible to measur...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
Inventor 何志君
Owner CHINGIS TECH CORP