igbt collector structure

Abstract

The invention provides an IGBT (Insulated Gate Bipolar Translator) collection electrode structure, comprising a N<-> type base region and further comprising N<+> type region layers which are distributed on the back face of the N<-> type base region at intervals, wherein P<+> type collection electrode layers are distributed on uncovered regions of the N<+> type region layers at intervals, which are distributed at intervals. The N<+> type region layers which are distributed at intervals are formed by injecting pentads from the back face of the N<-> type base region at intervals and carrying out all heat processes of the front face of the N<-> type base region. Or, the N<+> type region layers which are distributed at intervals are obtained by epitaxially growing one layer of the N<+> type layer on the back face of the N<-> type base region, carrying out interval etching and carrying out all the heat processes of the front face of the N<-> type base region. The invention provides the collection electrode structure for forming an IGBT.

Description

technical field [0001] The invention relates to a structure of an electronic component, in particular to an IGBT collector structure. Background technique [0002] IGBT: The acronym for Insulated Gate Bipolar Transistor, a voltage-controlled power device that is widely used as a high-voltage switch. Generally, according to the depletion of the electric field in the drift region, it is divided into punch-through type and non-punch-through type, and then field cut-off type appears with the development of the process. Such as figure 1 As shown, it is a non-punch-through (NPT) device, and its chip design thickness is relatively thick, resulting in a high saturation conduction voltage drop Vce(sat) of the device, and when the device is turned off, there is a carrier recombination process. If the time is longer, the dynamic and static performance of the device will be poor. However, the saturated conduction voltage drop of this device increases with the increase of temperature ...

AI Technical Summary

Problems solved by technology

like figure 2 As shown, it is a field-stop (FS) device, due to the introduction of the N+ buffer layer ( figure 2 2) to cut off the electric field, the thickness of the chip design is thinner, the Vce(sat) and switching performance of the device are better than that of the NPT device, but the N+ buffer layer is passed on the back after the front process is completed. The high-energy injection and annealing of pentavalent elements requires high equipment and high process requirements, and it is more complicated to implement. In addition, the short-circuit resistance of FS-type devices is worse than that of NPT-type devices. Although Vce(sat) is also a positive temperature coefficient, But not as good as NPT type devices, less suitable for parallel applications

Images