Transmission line structure capable of eliminating DDR3 (Double Data Rate 3) load difference influence as well as forming method and internal storage structure thereof

Abstract

The invention provides a transmission line structure capable of eliminating DDR3 (Double Data Rate 3) load difference influence as well as a forming method and an internal storage structure thereof. The forming method comprises the following steps of: determining intrinsic parameters of a first-type transmission line and a second-type transmission line; determining first equivalent parameters of the first-type transmission line according to the intrinsic parameters of the first-type transmission line and the load capacity of a first load; determining second equivalent parameters of the second-type transmission line according to the intrinsic parameters of the second-type transmission line and the load capacity of a second load; determining the target delay of the first-type transmission line under the first load according to the first equivalent parameters; regulating the second equivalent parameters to third first equivalent parameters, so as to enable the equivalent delay of the second-type transmission line under the second load to be matched with the target delay of the first-type transmission line under the first load; and forming a basic transmission line and a special transmission line respectively based on the first equivalent parameters and the third equivalent parameters, wherein the basic transmission line and the special transmission line constitute the transmission line structure. By utilizing the technical scheme, the time sequence integrality of signals in signal transmission is improved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a transmission line structure and a forming method for eliminating the influence of DDR3 load differences, and a memory structure. Background technique [0002] Memory is one of the most important components in a computer. All programs in the computer run in the memory, so the performance of the memory has a great impact on the computer. The memory generally adopts semiconductor storage unit, including random access memory (RAM), read-only memory (ROM) and high-speed cache (Cache). Among them, random access memory is the most important memory, and the computer's CPU can read data from it, and can also write data, but when the computer is turned off, the data stored in it will be lost. With the development of technology, the access speed and capacity of random access memory are constantly increasing. [0003] Nowadays, Synchronous Dynamic Random Access Memory (SDRAM) is widely us...

AI Technical Summary

Problems solved by technology

Usually, in the transmission of address / command / control / clock signal of DDR3, a transmission line structure in the form of serial push is used to transmit the signal sent by the memory controller to the memory module, but due to different types of signal driven signals The number of loads (that is, the number of memories) is different. For example, the load driven by the address / command signal is more, and the load driven by the control / clock signal is less. Such a load difference will cause a difference in signal transmission delay skew

[0005] For more technical solutions about memory and transmission line structure, please refer to the US patent application document with publication number US2007263475A1: Transmission of data signal control signal of DDR2 SDRAM using common mode differential (Using Common Mode Differential Data Signals Of DDR2 SDRAM For Control Signal Transmission ), but also did not solve the above problem

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