Sampling method for analog-to-digital conversion chip

Abstract

The invention discloses a sampling method for an analog-digital conversion chip. The sampling method for the analog-digital conversion chip comprises the steps of (1) allocating a general purpose input or output (GPIO) pin according to the Ready signals of the analog-digital conversion chip, arranging the Ready signals to be triggered when falling edge exists, (2) allocating a extended direct memory access (EDMA) parameter table, receiving and sending events by an enabled serial peripheral interface_ direct memory adapter (SPI_DMA) and stopping the events by an GPIO in an event enabled register, and allocating a channel parameter table corresponding to the events, (3) arranging a serial peripheral interface (SPI) module of a digital signal processor (DSP)to be a master module, arranging enabled SPI_DMA module, and arranging SPI clock frequency, (4) enabling analog-digital (AD) sampling, and automatically placing sampling data into a data buffer. The sampling method for the analog-digital conversion chip has the advantages of consuming no central processing unit (CPU) in the process of sampling, greatly improving efficiency of a system performing application programs, ensuring real-time performance and continuity of data without losing data when sampling is stopped, and meanwhile being simple and reliable in operation.

Description

technical field [0001] The invention relates to a continuous automatic sampling method of an analog-to-digital conversion chip based on DMA and SPI communication ports. Background technique [0002] At present, there are many ADC chips using SPI communication on the market. For example, Ti’s ADS1178 has the following problems when communicating with IT company’s C6000 series DSP: 1) The SPI interrupt method is used to receive sampling data, and there is a problem of high interrupt rate. (The interrupt speed is 6-8 times the sampling rate), and the interrupt overhead is large. 2) Using TI's C6000 serial DSP chip, because its library function will prohibit any interrupt response after entering the pipeline, this will definitely cause the loss of sampling points, resulting in serious consequences. 3) Adding a piece of CPLD or FPGA for timing conversion or dedicated sampling will greatly increase the design cost. Contents of the invention [0003] The purpose of the present ...

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Problems solved by technology

[0002] At present, there are many ADC chips using SPI communication on the market. For example, Ti’s ADS1178 has the following problems when communicating with IT company’s C6000 series DSP: 1) The SPI interrupt method is used to receive sampling data, and there is a problem of high interrupt rate. (The interrupt speed is 6-8 times the sampling rate), the interrupt overhead is large

2) Using TI's C6000 sequence DSP chip, because its library function will prohibit any interrupt response after entering the pipeline, this will definitely cause the loss of sampling points, resulting in serious consequences

3) Adding a CPLD or FPGA for timing conversion or dedicated sampling will greatly increase the design cost

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