Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Multiplying unit structure for discrete cosine transformation (DCT)/inverse discrete cosine transformation (IDCT) circuit under high efficiency video coding (HEVC) standard

A technology of multipliers and circuits, which is applied in calculations using number system representations and calculations using non-contact manufacturing equipment, etc., can solve the problems of large computing resource occupation and long computing time, and reduce power consumption and chip area. The effect of improving computing speed and streamlining hardware resources

Inactive Publication Date: 2013-05-08
SHANGHAI JIAO TONG UNIV
View PDF1 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such an algorithm has disadvantages such as long operation time and high operation resource occupation in the circuit design method.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multiplying unit structure for discrete cosine transformation (DCT)/inverse discrete cosine transformation (IDCT) circuit under high efficiency video coding (HEVC) standard
  • Multiplying unit structure for discrete cosine transformation (DCT)/inverse discrete cosine transformation (IDCT) circuit under high efficiency video coding (HEVC) standard
  • Multiplying unit structure for discrete cosine transformation (DCT)/inverse discrete cosine transformation (IDCT) circuit under high efficiency video coding (HEVC) standard

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0053] 1) Usually, the multiplier for realizing constant multiplication operation can be realized by shift-add operation, so the shift-add circuit design is the basis of the present invention. The shift-and-add algorithm of general integer multiplication is realized by the method of unit shift-add. The constant multiplication parameter used by DCT / IDCT is a 7-bit integer, which is applied to the general shift-add circuit structure, using 6 shift operations and 6 According to the usual design principles, it is estimated that a shift and an addition take one cycle for one addition operation, and a general shift and addition circuit needs to take at least 6 cycles to complete the operation. In the circuit design method, such an algorithm has disadvantages such as a long operation time and a large occupation of operation resources.

[0054] 2) By studying the constant multiplication operation process used by DCT / IDCT, analyzing the characteristics of the constant value used in the...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a multiplying unit structure for a discrete cosine transformation (DCT) / inverse discrete cosine transformation (IDCT) circuit under a high efficiency video coding (HEVC) standard. The multiplying unit structure comprises a preprocessing operation module, a primary shifting adding operation module and a secondary shifting adding operation module which are connected in series in sequence. A pre-operation unit is provided with a data input port and a parameter input port. The secondary shifting adding operation module is provided with an operation result output port. Compared with the prior art, the multiplying unit structure has the advantages of being capable of meeting system functions, having smaller occupancy of hardware resource and faster operation cycle, and the like.

Description

technical field [0001] The invention relates to the field of digital integrated circuits, in particular to a multiplier structure used for DCT / IDCT circuits under the HEVC standard. Background technique [0002] 1. Development background of video codec standards [0003] With the continuous expansion and deepening of the application range of multimedia technology in the military and civilian fields, especially with the continuous development of consumer electronics products, video codec technology has become a research field that has attracted much attention in the world. Video codec technology is the main technology for building and playing video, and the fundamental technology for all video applications. [0004] With the continuous improvement of video resolution, high-definition, ultra-high-definition and even 4K full-high-definition video resolutions are gradually entering the application link. The ever-increasing video scale poses a huge challenge to the implementatio...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F7/52
Inventor 洪亮朱惠何卫锋李琛毛志刚
Owner SHANGHAI JIAO TONG UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com