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A clamping voltage generating circuit
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A technology for generating circuits and clamping voltage, which is applied in the field of clamping voltage generating circuits, and can solve problems such as no power supply voltage and non-adjustable proportional coefficients
Active Publication Date: 2016-11-09
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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[0003] According to the type characteristics of SA, in order to improve the performance of the "read" operation of SA at different power supply voltages and different process angles, the gate voltage needs to rise according to a certain proportional coefficient with the rise of the circuit power supply voltage VDD. The absolute value of Vt (threshold voltage) increases and decreases according to a certain proportional coefficient. The existing clamping BL voltage circuit either has no power supply voltage and process corner compensation, or has compensation but the proportional coefficient cannot be adjusted.
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no. 1 example
[0048] Such as image 3 As shown, the first embodiment of the clamping voltage generating circuit of the present invention includes:
[0049] Operational amplifier A1, its inverting input terminal is connected to the reference voltage Vref, its non-inverting input terminal is internally grounded through the resistor R1, and its output terminal is connected to the gates of PMOS transistor P1 and PMOS transistor P2;
[0050] The power supply voltage VDD is connected to the sources of PMOS transistor P1, PMOS transistor P2 and PMOS transistor P3;
[0051] The drain of the PMOS transistor P1 is internally grounded through the series connected resistor R2 and resistor R1;
[0052] The drain of the PMOS transistor P2 is connected to the drain of the NMOS transistor N1;
[0053] PMOS transistor P3, its gate and drain are short-circuited and grounded internally through the series connected resistor R4 and resistor R3;
[0054] The NMOS transistor N1, its gate and drain are short-ci...
no. 4 example
[0068] Such as Figure 6 As shown, the fourth embodiment of the clamping voltage generating circuit of the present invention includes:
[0069] Operational amplifier A1, its inverting input terminal is connected to the reference voltage Vref, its non-inverting input terminal is internally grounded through the resistor R1, and its output terminal is connected to the gates of PMOS transistor P1 and PMOS transistor P2;
[0070] The power supply voltage VDD is connected to the source of PMOS transistor P1 and PMOS transistor P2, and is internally grounded through the series connected resistor R4 and resistor R3
[0071] The drain of the PMOS transistor P1 is internally grounded through the series connected resistor R2 and resistor R1;
[0072] The drain of the PMOS transistor P2 is connected to the drain of the NMOS transistor N1;
[0073] The NMOS transistor N1, its gate and drain are short-circuited and then connected to the circuit output terminal OUT, and its source is inter...
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Abstract
The invention discloses a clamping voltage generation circuit. The clamping voltage generation circuit comprises 1, an operational amplifier A1, wherein an inverting input terminal of the operational amplifier A1 is connected to reference voltage; a non-inverting input terminal of the operational amplifier A1 is internally connected to the ground by a resistance R1; and an output terminal of the operational amplifier A1 is connected to grids of a PMOS pipe P1 and a PMOS pipe P2, 2, a supply voltage VDD, wherein the supply voltage VDD is connected to source electrodes of the PMOS pipe P1, the PMOS pipe P2 and a PMOS pipe P3, 3, the PMOS pipe P1, wherein a drain electrode of the PMOS pipe P1 is internally connected to the ground by a resistance R2 and the resistance R1 connected in series, 4, the PMOS pipe P2, wherein a drain electrode of the PMOS pipe P2 is connected to a source electrode of an NMOS pipe N1, 5, the PMOS pipe P3, wherein a grid electrode of the PMOS pipe P3 is in a short circuit connection relationship with its drain electrode and then is internally connected to the ground by a resistance R4 and a resistance R3 connected in series, and 6, the NMOS pipe N1, wherein a grid electrode of the NMOS pipe N1 is in a short circuit connection relationship with its drain electrode and then is connected to a circuit output terminal; and the source electrode of the NMOS pipe N1 is internally connected to the ground by the resistance R3. The clamping voltage generation circuit can improve performances of a reading process of a sense amplifier (SA) under different source voltages and at different process angles.
Description
technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a clamping voltage generating circuit. Background technique [0002] In a non-volatile memory integrated circuit, in order to reduce the impact of the "read" operation on the performance of the memory cell (read disturbance), it is necessary to limit the potential of the BL (Bit Line, bit line), so a clamping circuit is required. The general method of clamping the BL voltage is to add an N tube (such as figure 1 shown), clamp the BL voltage by limiting the gate voltage or use an inverter to clamp the BL potential (such as figure 2 shown). [0003] According to the type characteristics of SA, in order to improve the performance of the "read" operation of SA at different power supply voltages and different process angles, the gate voltage needs to rise according to a certain proportional coefficient with the rise of the circuit power supply voltage V...
Claims
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Application Information
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