ROM (Read Only Memory) and layout thereof
A memory and layout technology, applied in the field of integrated circuits, can solve the problems of large unit information storage area and shrinkage of ROM basic storage units, and achieve the effect of reducing the storage area
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[0032] Example one:
[0033] This embodiment provides a ROM memory, including: at least one MOS transistor, a bit line, and a word line, where figure 1 As shown, the drain of each MOS transistor corresponds to at least two bit lines BL, the gate of the MOS transistor is connected to the word line WL, and the source of the MOS transistor is grounded.
[0034] The connection state of two or more bit lines and the MOS tube can make the MOS tube store more than two kinds of state information. That is, under the premise of a certain ROM memory area, by increasing the number of bit line regions, the programmable information of a MOS tube of the ROM memory can be made larger than 1 bit, and the storage area of 1 bit information is correspondingly reduced.
Example Embodiment
[0035] Embodiment two:
[0036] This embodiment discloses a ROM memory layout corresponding to the above embodiment, which includes at least one MOS tube area, a word line area and a bit line area.
[0037] Among them, such as figure 2 As shown, the MOS tube region source region S, source metal region SM, drain region D, drain metal region DM, gate region G, and gate metal region GM. The source metal region SM, the drain metal region DM and the gate metal region GM all extend in a first direction and are arranged in a second direction, the first direction being perpendicular to the second direction. And the source metal region SM is located in the source region S, the drain metal region DM is located in the drain region D, the gate metal region GM is located in the gate region G, between the source metal region SM and the source region S A contact hole is provided between the drain metal region DM and the drain region D, and between the gate metal region GM and the gate region G,...
Example Embodiment
[0043] Embodiment three:
[0044] This embodiment discloses another ROM memory, which includes a MOS tube, a word line and three bit lines.
[0045] Such as image 3 As shown, the source of the MOS transistor is grounded, the gate is connected to the word line WL, and the drain corresponds to three bit lines, namely the first bit line BL1, the second bit line BL2, and the third bit line BL3.
[0046] Among them, the first bit line BL1, the second bit line BL2, and the third bit line BL3 can only have one connected to the drain of the MOS transistor. When the third bit line BL3 is connected to the drain, one MOS transistor stores When the second bit line BL2 is connected to the drain, the state information stored by a MOS transistor is “01”; when the first bit line BL1 is connected to the drain, a MOS transistor The stored state information is "10"; when no bit line is connected to the drain, the state information stored by a MOS tube is "11".
[0047] Figure 4 For the layout of the ...
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