Two-port static random access memory using single-port memory unit

Abstract

The invention provides a two-port static random access memory which uses single-port memory units. The two-port static random access memory mainly comprises a writing drive, a writing bit line selector, a writing column decoder, a writing control circuit, a writing self-timing module, a sense amplifier, a reading bit line selector, a bit line pre-charger, a reading sense amplifier, a reading control circuit, a reading self-timing module, a row decoder and a memory unit array, wherein according to input reading and writing line addresses, the row decoder sequentially generates reading and writing word line signals within one period; according to reading and writing column addresses, the reading and writing column decoders respectively generate reading and writing bit line selection signals; and the reading and writing control circuits respectively generate control signals necessary for reading and writing operation. According to the design of the two-port static random access memory, a read-write port multiplexing technique is utilized and conventional six-tube memory units are used, thereby realizing functions of a two-port memory unit; and compared with the conventional design based on the two-port memory unit, the design is reduced by nearly 50% in area.

Description

【Technical field】 [0001] The invention relates to the field of static random access memory design, in particular to a two-port static random access memory. 【Background technique】 [0002] With the rapid growth of the market of mobile terminals, such as smart phones and tablet PCs, the performance of video processing engines (such as running speed, precision of digital images) has been significantly improved. Among these processors, two-port static random access memory (2P-SRAM) is widely used. This memory allows simultaneous operation of a read port and a write port within one clock cycle. [0003] According to the forecast of the International Semiconductor Technology Roadmap (ITRS), the area of ​​SRAM will become larger and larger, and by 2013, it will account for more than 90% of the area of ​​the entire system-on-chip (SOC). For real-time video processing SOC, this trend is more obvious. An H.264 decoder for high-definition digital TV decoding requires at least 500k-b...

AI Technical Summary

Problems solved by technology

Doubling the length of the word line will result in a quadrupling of the time constant (RC) due to word line parasitics, thereby increasing the delay of the word line due to parasitics

The word line is usually on the critical path of the read access operation of the static memory, so the increase of the word line delay also increases the read access time

[0005] Therefore, it is challenging to design a two-port SRAM with high area efficiency and fast read access time

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