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Wafer test method

A wafer testing and wafer technology, applied in the direction of semiconductor/solid-state device testing/measurement, etc., can solve the problem of small chip area, and achieve the effect of reducing cost and test time

Active Publication Date: 2015-05-27
NANJING ZGMICRO CO LTD
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Problems solved by technology

[0003] However, with the improvement of circuit design technology, the chip area is getting smaller and smaller. For example, 160,000 chips may be produced on an 8-inch wafer. If the test time of each chip is 250mS, it takes 40,000 seconds to test a wafer. , takes about 11+ hours
If the test fee is calculated at US$12 per hour, the test cost is about US$133. If the wafer manufacturing cost is US$270, the wafer testing cost accounts for about half of the wafer manufacturing cost.

Method used

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Embodiment Construction

[0014] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0015] Reference herein to "one embodiment" or "an embodiment" refers to a particular feature, structure or characteristic that can be included in at least one implementation of the present invention. "In one embodiment" appearing in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words connected, connected, and joined in this document mean that they are electrically connected directly or indirectly.

[0016] The purpose of wafer testing is to screen out chips with incorrect functions (Die) on the wafer, which can also be called bad chips, bad chips or abnormal chips. In...

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Abstract

The invention provides a wafer test method which includes the steps: setting an abnormal wafer map for a wafer; and testing each normal wafer area on the wafer to be tested according to the abnormal wafer map including abnormal wafer areas on the wafer while skipping over testing the abnormal wafer areas. Compared with the prior art, the wafer test method has the advantages that the abnormal wafer map is generated for each wafer, the abnormal wafer areas can be directly skipped over when the wafer is tested, accordingly, wafer passing time and performance test time for the abnormal wafer areas are saved, and the cost of a chip is reduced.

Description

【Technical field】 [0001] The invention relates to the field of wafer testing, in particular to a wafer testing method. 【Background technique】 [0002] Chip (or wafer) manufacturing generally goes through many production processes such as wafer (Wafer) manufacturing, wafer testing, cutting, packaging, and finished product testing. Among them, the purpose of the wafer test is to screen out the dies with incorrect functions on the wafer, and the dies with incorrect functions may also be called bad dies, bad dies or abnormal dies. In the prior art, during wafer testing, each chip on the wafer is tested by automatic testing equipment, unqualified chips are marked with ink dots, and these bad chips are not packaged during packaging. If the bad chips are packaged, then Increased packaging cost. Wafer testing time can be divided into film-running time and performance testing time. Among them, the chip running time refers to the time it takes to move the probes that touch the test...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
Inventor 王钊田文博尹航
Owner NANJING ZGMICRO CO LTD
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