Semiconductor device and operating method thereof

Abstract

The invention discloses a semiconductor device and operation methode for the same. The semiconductor device includes an internal voltage input buffer configured to determine voltage levels of a pull-up driving node and a pull-down driving node as a result of a comparison between a voltage level of an internal voltage node and a voltage level of a reference voltage node such that the pull-up driving node and the pull-down driving node to maintain a voltage level difference, and an internal voltage driving block configured to pull-up drive the internal voltage node in response to the voltage level of the pull-up driving node and pull-down drive the internal voltage node in response to the voltage level of the pull-down driving node.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2011-0130951 filed on December 8, 2011, the entire contents of which are hereby incorporated by reference. technical field [0003] Exemplary embodiments of the present invention relate to a semiconductor design technology, to an internal voltage generating circuit of a semiconductor device and an operating method thereof, and more particularly, to a semiconductor device not including a dead zone operating region Internal voltage generating circuit and method of operation thereof. Background technique [0004] As critical dimensions and cell sizes of semiconductor devices decrease, supply voltages are also reduced, and therefore, design techniques for low voltage environments are useful. [0005] For example, a semiconductor device includes an internal voltage generating circuit that receives a power supply voltage (VDD) and generates an internal v...

AI Technical Summary

Problems solved by technology

[0022] If the punch-through current phenomenon occurs in this way, the current usage of the semiconductor device suddenly increases, and thus, the power consumption of the semiconductor device increases, therefore, in the prior art, a dead zone equal to or greater than several tens of mV is maintained

[0023] Therefore, the reaction speed of the internal voltage generating circuit is basically lowered due to the existence of the dead area, and the performance of the semiconductor device may deteriorate

Images