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Heatsinks for Integrated Circuits Integrated Power Delivery and Distribution

A heat sink and power technology, applied in the direction of circuits, electrical solid state devices, electrical components, etc., can solve problems such as design constraints

Active Publication Date: 2016-01-13
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For 3D chip stacking, this creates severe design constraints and reduces possible performance gains from vertical integration

Method used

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  • Heatsinks for Integrated Circuits Integrated Power Delivery and Distribution
  • Heatsinks for Integrated Circuits Integrated Power Delivery and Distribution
  • Heatsinks for Integrated Circuits Integrated Power Delivery and Distribution

Examples

Experimental program
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Embodiment Construction

[0011] One example embodiment provides a mechanism for optimizing semiconductor packages in a 3D stack by dedicating one side of the three-dimensional (3D) stack to power delivery and the other side of the 3D stack to high speed signaling delivery. Then, power delivery and high-speed signaling for 3D stacking are addressed by using through-silicon vias (TSVs). In another example embodiment, the delivery of the multiple power voltages required for the 3D stack is provided via a heat sink that provides integrated power delivery and distribution to the various integrated circuits of the 3D stack.

[0012] Accordingly, the example embodiments are utilized in many different types of data processing environments, including distributed data processing environments, a single data processing device, and the like. In order to provide a context for describing the specific elements and functions of the example embodiments, the following provides figure 1 As an example environment in whic...

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Abstract

A mechanism for integrated power delivery and distribution via a heat sink is provided. The mechanism includes: a processor layer coupled to a signaling and input / output (I / O) layer via a first set of coupling devices; and a heat sink coupled to the processor layer via a second set of coupling devices. In this mechanism, the heat sink includes a plurality of slots on one side, where each slot provides a path for delivering power to the processor layer or a path for delivering ground to the processor layer. In this mechanism, the heat sink is only used to deliver power to the elements of the mechanism and not to provide data communication signals to the elements, and the signaling and I / O layers are only used to transfer data communication signals to and from the processor layer. Data communication signals are received without providing power to elements of the processor layer.

Description

technical field [0001] The present application relates generally to an improved data processing apparatus and method, and more particularly to mechanisms for integrated power delivery and distribution to integrated circuits via heat sinks. Background technique [0002] Three-dimensional (3D) integration provides increased performance for microprocessor architectures through increased interconnectivity between layers within a chip stack. However off-stack electrical connectivity (signal and power) is still implemented on only one surface of the chip stack and does not scale with the number of layers. With further upgrades of Complementary Metal Oxide Semiconductor (CMOS) transistors, the C4 number will not be enough even for a single die due to the slow decrease in C4 pitch over time. For 3D chip stacking, this creates severe design constraints and reduces possible performance gains from vertical integration. Contents of the invention [0003] In one embodiment, a three-d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/18
CPCH01L23/3672H01L25/18H01L2225/06527H01L2225/06589H01L2924/0002Y10T29/49002H01L2924/00H01L23/50
Inventor H·巴罗斯基A·胡贝尔H·哈雷尔T·尼格迈尔J·祖佩尔B·米歇尔T·布伦斯奇维勒S·帕雷德斯
Owner GLOBALFOUNDRIES INC