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vertical bjt and scr for esd

An ESD protection and direct technology, applied in electrical components, transistors, thyristors, etc., to solve problems such as abnormal operation of electronic products and permanent damage to integrated circuits

Active Publication Date: 2016-02-24
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If EOS occurs due to ESD, unprotected integrated circuits (ICs) in electronic devices and systems may cause permanent damage, and any damage to ICs in electronic devices or systems can cause abnormal operation of electronic products

Method used

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Embodiment Construction

[0036] The making and using of preferred embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0037] The present invention will be described with reference to a preferred embodiment in the specific context of an electrostatic discharge (ESD) protection device formed using a Fin Field Effect Transistor (FinFET) Complementary Metal Oxide Semiconductor (CMOS) process flow. However, the invention is also applicable to other types of semiconductor structures or circuits.

[0038] Also refer to Figure 1a to Figure 1b , shows an ESD protection device 10 . As will be explained more fully below, the ESD protection device 10 may be used to protect electronic de...

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PUM

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Abstract

An electrostatic discharge (ESD) protection device is provided. The ESD includes a well region formed of a semiconductor material having a first doping type and a floating base formed of a semiconductor material having a second doping type. The floating base is vertically arranged above the well region. The ESD also includes a first termination receiving region formed of a semiconductor material having a third doping type. The first terminal receiving area is vertically arranged above the floating base. The ESD also includes a second terminal receiving area. The second receiving terminal area is horizontally and laterally separated from the first receiving terminal area by a shallow trench isolation (STI) area. In some embodiments, the second terminal receiving region is formed of a semiconductor material having a third doping type to form a bipolar junction transistor (BJT). In some embodiments, the second terminal receiving region is formed of a semiconductor material having a fourth doping type to form a silicon controlled rectifier (SCR). The present invention provides vertical BJTs and SCRs for ESD.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly to electrostatic discharge (ESD) protection devices and methods of forming the same. Background technique [0002] Semiconductor devices are used in a large number of electronic devices, such as computers, mobile phones, and others. Semiconductor devices include integrated circuits formed on semiconductor wafers by depositing and patterning thin films of many types of materials over the semiconductor wafers. Integrated circuits include field effect transistors (FETs), such as metal oxide semiconductor (MOS) transistors. [0003] One of the goals of the semiconductor industry is to continue to shrink the size and increase the speed of individual FETs. To achieve these goals, fin-shaped FETs (FinFETs) or multi-gate transistors will be used at sub32nm (sub32nm) transistor nodes. For example, FinFETs not only increase areal density but also improve gate control of the channel....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L29/73H01L29/74
CPCH01L29/74H01L29/732H01L27/0262H01L27/04
Inventor 林文杰娄经雄曾仁洲
Owner TAIWAN SEMICON MFG CO LTD
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