Line-speed processing cell method and device of automatic teller machine (ATM) multiple service access exchange board

Abstract

The invention relates to a line-speed processing cell method and a device of an automatic teller machine (ATM) multiple service access exchange board. The line-speed processing cell device of the ATM multiple service access exchange board is achieved based on an FPGA. The line-speed processing cell device comprises an entrance switching VPI/VCI state machine and an exit VPI/VCI state machine. An entrance reception FIFO queue and an entrance emission FIFO queue are arranged in a cell entrance direction of each physical port. An exit emission FIFO queue and an exit reception FIFO queue are arranged in a cell exit direction. The entrance switching VPI/VCI state machine reads a cell from the entrance reception FIFO queue which is not empty. Cells which are switched are written into the exit emission FIFO queue. The ATM exchange board can perform line-speed cell processing and provide processing rate and handling capacity of data.

Description

technical field [0001] The invention relates to a method and device for processing cells at a line speed in an ATM multi-service access switch, and belongs to the technical field of ATM switching. Background technique [0002] The ATM multi-service access switch is mainly composed of a switching chip and a framing chip to realize the exchange of ATM cells between each service sub-card and an ATM uplink port. In practical applications, the switch chip has the following restrictions: If the number of logical ports supported by the switch chip is PID, its occupied bit width is NPID, the occupied bit width of VPI is NVPI, and the bit width occupied by VCI is NVCI, then it needs to meet: NPID+NVPI +NVCI=16bit. For example, if the switch chip supports 30 logical ports, 5 bits are required for the port base address, and only 11 bits are left for NVPI+NVCI. It can be seen that the values ​​of the virtual path indicator VPI and virtual channel indicator VCI available for the virtual...

AI Technical Summary

Problems solved by technology

[0007] 3) The VPI / VCI is split and mapped so that the external VPI / VCI cannot truly achieve arbitrary configuration

[0008] 4) Only the case of building a VCC is considered, and the case of building a VPC is not considered

[0009] 5) The mapping between internal VPI / VCI and external VPI / VCI of multiple ports is not considered

[0010] 6) It does not take into account that the NPID, NVPI, and NVCI of the switch chip are configurable and changeable

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