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Systems and methods for photolithographic patterning

A lithography system and lithography technology, applied in the field of semiconductors, can solve problems such as inaccurate measurement and low efficiency

Active Publication Date: 2016-08-03
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Also, existing alignment measurements are inaccurate and less efficient

Method used

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  • Systems and methods for photolithographic patterning
  • Systems and methods for photolithographic patterning
  • Systems and methods for photolithographic patterning

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Embodiment Construction

[0036] It is to be understood that the following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. Additionally, the present invention may repeat reference numerals and / or letters in multiple instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0037] figure 1 is a schematic diagram of a lithographic system 20 for performing various lithographic patterning processes constructed in accordance with aspects of the present invention. refer to figure 1 Together with the other figures, a lithographic system 20 and methods of using the same are described. Photolithography system 20 includes various process tools and metrology t...

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Abstract

Disclosed is a lithography system. The lithography system includes a lithography exposure tool designed for performing an exposure process to a radiation-sensitive material layer coated on an integrated circuit substrate; an alignment module coupled with the lithography exposure tool, designed for alignment measurement, and configured for transferring the integrated circuit substrate to the lithography exposure tool; and an alignment calibration module designed to calibrate the alignment module relative to the lithography exposure.

Description

technical field [0001] The present invention relates to the field of semiconductors, and more particularly, the present invention relates to a system and method for photolithographic patterning. Background technique [0002] Semiconductor integrated circuit (IC) technology has undergone rapid development, including continuous minimization of feature size and maximization of packaging density. Minimization of feature size relies on improvements in lithography and the ability to print smaller features or critical dimensions (CDs). This is further about wafer alignment. Perform wafer alignment in a lithography scanner. The scanner exposes the wafer based on the alignment results. To reduce overlay errors, improvements in alignment accuracy and overlay measurement accuracy results are required. However, during the photolithography process, the wafer may experience wafer bonding and deformation caused by wafer clamping (chucking) or other factors such as thermal processes. E...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F7/20G03F9/00
CPCG03F9/7096G03F9/7019
Inventor 陈立锐梁辅杰吴雪鸿
Owner TAIWAN SEMICON MFG CO LTD