Multivoltage clock synchronization

Abstract

A level converter circuit is disclosed. The level converter circuit includes a first level converter that generates a first output signal, and a second level converter that generates a second output signal. The level converter circuit further includes an edge selector coupled to the first level converter and the second level converter that selects a rising edge of either the first output signal or the second output signal, and selects a falling edge of either the first output signal or the second output signal to generate an optimized output signal.

Description

technical field [0001] The present invention relates generally to digital computer systems. Background technique [0002] Analog circuits often need to distribute clock signals to multiple voltage domains throughout their operation. A common situation is in CMOS analog-to-digital converters (ADCs) used in communication and video systems, where the input sampling switch is in the 2.5 / 3.3 volt domain and the core of the ADC is in the 1.2 volt domain. These two clock domains must be well aligned to allow high frequency operation with low sampling jitter and distortion. In fact, this misalignment is often one of the main sources of distortion in high speed ADCs. Under certain conditions, it may even be the decisive factor. [0003] figure 1 The circuit of ® is typically used to transfer the clock signal from the 1.2V domain (LV-low voltage) to the 2.5V or 3.3V domain (HV-high voltage). The PMOS transistors (M3 / M4) must be weaker than the underlying NMOS (M1 / M2) for proper o...

AI Technical Summary

Problems solved by technology

[0009] Embodiments of the invention address the problem of having to add a delay to the low voltage clock in order to align the low voltage clock with the high voltage clock

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