Test structure of transistor alternating current hot carrier injection characteristics

Abstract

The invention discloses a test structure of transistor alternating current hot carrier injection characteristics. The test structure comprises a PMOS P1 to be tested, an NMOS N1 to be tested and a test load N2. A grid electrode of P1 and a grid electrode of N1 are connected to serve as a test pin a of the test structure, a source electrode of the P1 serves as a test pin b of the test structure, a substrate electrode of the P1 serves as a test pin c of the test structure, a drain electrode of the P1 and a drain electrode of the N1 are connected to serve as a test pin d of the test structure, a substrate electrode of the N1 serves as a test pin e of the test structure, a source electrode of the N1 serves as a test pin of the test structure, one end of the test load N2 is connected with the test pin d, and the other end of the test load N2 is grounded to serve as a test pin g of the test structure. The test structure can accurately simulate the working state of a CMOS in a circuit, can accurately evaluate characteristic changes of the PMOS and the NMOS in the CMOS after the PMOS and the NMOS bear alternating current HCI stress, and can also evaluate characteristic changes of the CMOS after the CMOS bears the alternating current HCI stress.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a test structure for the AC hot carrier injection characteristics of a transistor. Background technique [0002] The current AC HCI (Hot Carrier Injection, Hot Carrier Injection) test structure is the same as the DC test structure, which is an independent PMOS or NMOS, or a structure with a common substrate electrode or (and) source electrode. When this independent structure is loaded with AC HCI stress, often only AC signals can be applied to one end (gate or drain), and the other end is a DC signal, which cannot truly simulate the working state of CMOS in the circuit, and cannot achieve the best evaluation. Effect. If AC signals are applied to the two ends (gate and drain) of the MOS device through two different devices, it is difficult to control whether the two signals are synchronized, so it is impossible to truly simulate the CMOS working state in the circuit, wh...

AI Technical Summary

Problems solved by technology

When this independent structure is loaded with AC HCI stress, it can only load an AC signal on one end (gate or drain), and the other end is a DC signal, which cannot truly simulate the working state of the CMOS in the circuit and cannot achieve the best evaluation. Effect

If AC signals are applied to the two ends (gate and drain) of the MOS device through two different devices, it is difficult to control whether the two signals are synchronized, so it is impossible to truly simulate the CMOS working state in the circuit. best evaluation effect

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