Low dropout regulator (LDO) and power supply rejection ratio (PSRR) improving method thereof

A low-dropout voltage stabilization and low-dropout linear technology, which is applied in the direction of instruments, electric variable adjustment, control/regulation systems, etc., can solve the problems of large PSRR drop, failure to reach, and failure to meet design needs, and achieve a significant increase in PSRR , the effect of increasing the gain

Inactive Publication Date: 2013-11-13
FAIRCHILD SEMICON SUZHOU
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Problems solved by technology

However, when the small signal frequency of the input voltage of this LDO is higher than 100KHz, the PSRR often cannot meet the ideal requirements, especially wh

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  • Low dropout regulator (LDO) and power supply rejection ratio (PSRR) improving method thereof
  • Low dropout regulator (LDO) and power supply rejection ratio (PSRR) improving method thereof
  • Low dropout regulator (LDO) and power supply rejection ratio (PSRR) improving method thereof

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Embodiment Construction

[0017] The basic idea of ​​the present invention is: a PSRR boosting circuit is set in the LDO, and when the input voltage has a high-frequency small signal, the PSRR boosting circuit amplifies the high-frequency small signal and transmits it to the output gain node of the low-dropout voltage regulator circuit , increase the gain of the low dropout voltage regulator circuit, thereby improving the PSRR of the LDO.

[0018] Here, the high-frequency small signal refers to a small signal with a frequency higher than 100KHz.

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] An LDO provided by an embodiment of the present invention, such as figure 2 As shown, the LDO includes: PSRR improving circuit 21 and low dropout voltage stabilizing circuit 22, wherein,

[0021] The PSRR improving circuit 21 is configured to amplify the high-frequency small signal when the input voltage has ...

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Abstract

The invention provides a low dropout regulator (LDO). The LDO comprises a power supply rejection ratio (PSRR) improving circuit and a low-voltage difference stabilizing circuit; and when the input voltage has a high-frequency small signal, the PSRR improving circuit amplifies the high-frequency small signal and transmits to an output gaining node of the low-voltage difference stabilizing circuit so as to increase the gain of the low-voltage difference stabilizing circuit. The invention also provides a PSRR improving method of the LDO. Through the scheme provided by the invention, under the condition that the zero/pole point of the low-voltage difference stabilizing circuit is not influenced, the PSRR of the LDO when the input voltage has the high-frequency small signal is improved, and the PSRR of the LDO is more obviously improved particularly when the frequency of the small signal is higher than 100 KHz.

Description

technical field [0001] The invention relates to a low dropout linear regulator technology, in particular to a low dropout linear regulator (LDO, Low Dropout regulator) and a method for improving a power supply rejection ratio (PSRR). Background technique [0002] When the input voltage is very close to the output voltage, LDO is usually selected for DC-to-DC conversion. The current LDO generally only guarantees that the power supply rejection ratio (PSRR) reaches above 50dB when the small signal frequency of the input voltage is lower than 10KHz, and when the small signal frequency of the input voltage is higher than 100KHz, the PSRR often drops below 40dB. [0003] figure 1 for an LDO, such as figure 1 As shown, the positive input terminal of the error amplifier (EA, Error Amplifier) ​​receives the reference voltage Vref, the negative input terminal is connected to the connection between the voltage dividing resistor R1 and the sampling resistor R2, and the output termina...

Claims

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Application Information

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IPC IPC(8): G05F1/56
Inventor 李东
Owner FAIRCHILD SEMICON SUZHOU
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