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Method for forming super thick insulating layer in through-silicon via through thermal oxidation

A technology for oxidizing insulating layers and through-silicon vias, applied in the field of microelectronics, can solve the problems of difficulty in forming a silicon oxide insulating layer and reducing the oxidation speed, and achieve the effects of improving reliability, reducing leakage current, and increasing the thickness of insulating layers.

Active Publication Date: 2015-02-25
NAT CENT FOR ADVANCED PACKAGING CO LTD
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Problems solved by technology

Silicon can be directly oxidized into silicon dioxide by thermal oxidation, but affected by the diffusion of oxygen atoms, when the thickness of the oxide layer exceeds 1 micron, the oxidation rate decreases a lot, and it is difficult to form a thicker silicon oxide insulating layer

Method used

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  • Method for forming super thick insulating layer in through-silicon via through thermal oxidation
  • Method for forming super thick insulating layer in through-silicon via through thermal oxidation
  • Method for forming super thick insulating layer in through-silicon via through thermal oxidation

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Embodiment Construction

[0025] figure 1 In the substrate 10, holes 101 and ring-shaped silicon regions 20 have been etched, and the holes 101 and ring-shaped silicon regions 20 are distributed concentrically. thick trend. The substrate 10 can be a silicon wafer with a size of 4-12 inches or larger, and the thickness can be 300-700 microns.

[0026] figure 2 30 in represents the oxidized insulating layer, that is, the state in which the ring-shaped silicon region 20 is oxidized and completely fills the ring-shaped region. The inner diameter of the annular silicon region 20, that is, the diameter of the hole 101 can be 5 microns to 50 microns, which can be adjusted according to the actual TSV size; the horizontal distance between the outer wall of the annular silicon region 20 and the silicon substrate can be 0.1-20 microns, so The thickness of the ring-shaped silicon region 20 can be 0.1-20 microns, which can be adjusted according to the required thickness of the oxide layer. The etching depth of...

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Abstract

The invention relates to a method for forming a super thick insulating layer in a through-silicon via through thermal oxidation, aiming at the problem that a thicker silicon oxide insulating layer is difficult to form since the oxidation speed is reduced greatly after the thickness of the oxide layer exceeds 1 micron in a process of producing the silicon dioxide insulating layer by a thermal oxidation method. According to the method, a hole (101) and an annular silicon region (20) are formed in a substrate (10); the annular silicon region (20) is distributed in the shape of a concentric circle around the hole (101); the side wall of the through-silicon via is etched to be annular; and then the annular silicon is oxidized to obtain the silicon oxide insulating layer. Considering the volume change proportion of silicon oxide formed in the through-silicon via, a periodic ring structure is formed through deep etching at a certain space, and the silicon ring is oxidized by using a thermal oxidation method to obtain the thickness of the required oxide layer. According to the method, the compact silicon oxide insulating layer with unlimited and controllable thickness can be obtained.

Description

technical field [0001] The invention relates to a method for manufacturing or processing semiconductor or solid devices in the technical field of microelectronics, in particular to a method for preparing a through-silicon hole insulating layer. Background technique [0002] As the feature size of the semiconductor process reaches the nanometer level, and the transistor is developing towards higher density and higher clock frequency, the limitations of the continuous proportional reduction of the integrated circuit are becoming more and more serious. Therefore, people are paying more and more attention to the development of higher density packaging, and high-density three-dimensional integration has become an important technical approach for system-level integration of microelectronics. Three-dimensional integration is a 3D high-density microelectronic package formed by further development towards the Z-axis direction on the basis of two-dimensional (X-Y plane) integration of...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 靖向萌于大全
Owner NAT CENT FOR ADVANCED PACKAGING CO LTD