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Phase-locked loop control voltage determination

A technology for controlling voltage and phase-locked loop, applied in the direction of automatic power control, electrical components, etc., can solve the problem of taking a long time and not being effective.

Inactive Publication Date: 2013-11-20
ERICSSON (CHINA) COMMUNICATION COMPANY LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, a typical PLL is not efficient for very low frequency clocks, such as 1 pulse per second signal (1PPS signal), i.e. it will take a long time before the output / feedback clock locks to the reference clock

Method used

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  • Phase-locked loop control voltage determination
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  • Phase-locked loop control voltage determination

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0019] figure 1 In , reference numeral 100 generally denotes a phase locked loop (PLL) circuit according to the present invention. The PLL includes a frequency detector (FD) 101 receiving a reference clock signal 102 and receiving a feedback clock signal 111 . The frequency detector outputs 107 an error signal to a control voltage calculator 103 (CTRL Volt. Calc.), which in turn is connected 108 to a digital-to-analog converter 104 . The converter 104 may in turn be connected 109 to a loop filter 105 which may be arranged between the converter 104 and a voltage controlled oscillator 106 (VCO). The VCO may for example be a voltage controlled crystal oscillator or an LC type oscillator. The VCO is in turn connected to a frequency detector and outputs a feedback clock signal 111 to the FD 101, and loops such as figure 1 shown to form. It should be noted that the loop filter 105 may be located between the control voltage calculator and the converter. It should also be noted t...

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PUM

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Abstract

A method and circuit is provided for determining a control voltage of a voltage controlled oscillator with fast frequency lock of a phase-locked loop and which is advantageous to the situation when an ultra-low frequency reference is used. The method and circuit determines a current error between a reference clock signal and a feedback clock signal, and checks if the error is larger than the threshold value which checks if an error sign indicator is set, i.e. the error has switched sign since startup of feedback loop; if the error sign indicator is not set, the circuit determines a divisor, kn, using the current error, en, current control voltage, un, previous error en-1, and previous control voltage, un-1; however, if the error sign indicator is set the circuit determines a divisor, kn, using stored values for the latest control voltage and error when the error was negative and stored values for the latest control voltage and error when the error was positive; furthermore, the method and circuit determines a control voltage step using the determined error divided by the divisor, kn, and determines a new control voltage using the current control voltage, un, and the determined control voltage step.

Description

technical field [0001] The invention relates to a method and a device for determining a control voltage of a phase locked loop. Background technique [0002] In many electronic control systems it is important to synchronize or couple two different signals to each other, for example this is of concern in radio, telecommunications and computers where the concerns are respectively stabilizing the frequency, recovering the signal and providing a clock timing signal. In these applications, the concern is to provide an output signal whose phase and / or frequency matches the reference signal. [0003] In telecommunications where different coding schemes are used, it is important to synchronize the communication data with the decoder in order to extract useful data. One of the components that is an integral part of this synchronization process is a Phase Locked Loop (PLL) device. [0004] For example, in telecommunications, phase-locked loops (PLLs) are used to generate clocks that...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L5/00H03L7/08
CPCH03L7/085H03L7/10H03L7/08H03L5/00H03L7/113
Inventor 文敢
Owner ERICSSON (CHINA) COMMUNICATION COMPANY LTD