Deblocking filter hardware on-chip storage method applicable to HEVC standard

Abstract

The invention belongs to the technical field of high definition digital video compression, encoding and decoding, and particularly provides a deblocking filter hardware on-chip storage method applicable to the HEVC standard. In an original video stream, each image comprises a luminance component Y, wherein each luminance component corresponds to two chrominance components, namely Cb and Cr. In a deblocking filter module, the deblocking filter hardware on-chip storage method is used for conducting processing on the basis of a quarter-LCU; the storage mode of an on-chip storage of the deblocking filter module comprises that the luminance components Y form a 9*9 square matrix and each chrominance component Cb and each chrominance component Cr respectively comprise 25 pixel blocks which form a 5*5 square matrix; the on-chip storage method is conducted on five SRAMs, namely the SRAM_L1, the SRAM_L2, the SRAM_C1, the SRAM_C2 and the SRAM_T, wherein the SRAMs respectively store all the pixel blocks of the Y, the Cb and the Cr according to a certain rule. The deblocking filter hardware on-chip storage method applicable to the HEVC standard can effectively improve the data reading capacity when a chip is used for data processing and shorten processing time, thereby efficiently realizing real-time coding of high definition videos.

Description

technical field [0001] The invention belongs to the technical field of high-definition digital video compression encoding and decoding, and is aimed at the HEVC video encoding and decoding standard, and in particular relates to a hardware on-chip storage method suitable for a deblocking filter of the HEVC standard. Background technique [0002] HEVC (High Efficiency Video Coding) is a next-generation video codec standard proposed by JCTVC, an organization jointly established by the International Telecommunications Organization (ITU) and the Motion Picture Experts Group (MPEG). The goal is to double the compression rate compared to the previous generation standard H.264 / AVC under the premise of the same visual effect. [0003] HEVC-based video encoder, its structure diagram is as follows figure 1 As shown, it is mainly composed of the following modules: intra prediction, inter prediction, transformation, quantization, inverse quantization, inverse transformation, reconstruct...

AI Technical Summary

Problems solved by technology

[0006] In hardware implementation, the different on-chip storage methods for the pixels to be processed will bring different processing time and hardware resources.

Images