A method for preparing sgoi or goi by using c-doped sige modulation layer
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A modulation layer and doping concentration technology, applied in the field of semiconductor material preparation, can solve problems such as lattice mismatch, affecting SGOI or GOI performance, defects, etc.
Active Publication Date: 2016-02-03
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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Problems solved by technology
However, in the process of making SGOI / GOI by the traditional Ge concentration process, due to the lattice mismatch between the SiGe / Si interface, it often causes a large number of defects at the interface, which greatly affects the performance of the final prepared SGOI or GOI.
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Embodiment 1
[0040] Such as Figure 1 to Figure 6 As shown, this embodiment provides a method for preparing SGOI or GOI using a C-doped SiGe modulation layer, at least including the steps:
[0041] Such as Figure 1 ~ Figure 2 As shown, step 1) is performed first, providing an SOI substrate including a silicon substrate 101 , a buried oxide layer 102 and a top silicon layer 103 , and forming a C-doped SiGe modulation layer 104 on the surface of the top silicon layer 103 .
[0042] As an example, in the C-doped SiGe modulation layer 104, the doping concentration of C is not less than 1E20 / cm 3 . In this embodiment, in the C-doped SiGe modulation layer 104 , the doping concentration of C is constant. Specifically, in the C-doped SiGe modulation layer 104, the doping concentration of C is 3E20 / cm 3 .
[0043] As an example, the thickness of the C-doped SiGe modulation layer 104 is not less than 20 nm and not greater than its critical thickness. In this embodiment, the C-doped SiGe modula...
Embodiment 2
[0056] Such as Figure 1 to Figure 6 As shown, this embodiment provides a method for preparing SGOI or GOI using a C-doped SiGe modulation layer, the basic steps of which are as in Embodiment 1, wherein, in the C-doped SiGe modulation layer 104, the doping concentration of C is not However, it gradually decreases from bottom to top, that is, the C concentration near the top silicon layer 103 is high, and the C concentration near the SiGe material layer 105 is low, so that the top silicon layer 103 of SOI and the epitaxial SiGe material can be better adjusted. The lattice mismatch between the layers 105 reduces the generation of defects.
[0057] As mentioned above, the present invention provides a method for preparing SGOI or GOI by using a C-doped SiGe modulation layer, including the steps: 1) providing an SOI substrate including a silicon substrate, a buried oxide layer and a top silicon layer, and on the top Forming a C-doped SiGe modulation layer on the surface of the sil...
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Abstract
The invention provides a method for preparing SGOI or GOI by utilizing a C adulteration SiGe preparing layer. The method comprises the first step of forming the C adulteration SiGe preparing layer on the surface of a top silicon layer of SOI, the second step of forming an SiGe material layer on the surface of the C adulteration SiGe preparing layer, the third step of forming an Si cap layer on the surface of the SiGe material layer, the fourth step of oxidizing annealing the structure to oxidize the Si cap layer and gradually oxidize the SiGe material layer, the C adulteration SiGe preparing layer and the top silicon layer to enable Ge in the SiGe material layer and the C adulteration SiGe preparing layer be diffused to the top silicon layer and gradually concentrated and forming a top SiGe layer or a top Ge layer and an SiO2 layer on the upward side, and the fifth step of removing the SiO2 layer. Lattice mismatch between the SOI top silicon layer and the epitaxial SiGe material layer is reduced through the C adulteration SiGe preparing layer, and accordingly defects produced in the process of concentration are reduced. The prepared SGOI has the advantages of being high in relaxation, low in defect density, high in Ge component and the like.
Description
technical field [0001] The invention relates to a method for preparing a semiconductor material, in particular to a method for preparing SGOI or GOI by using a C-doped SiGe modulation layer. Background technique [0002] With the rapid development of silicon-based large-scale integrated circuit technology, the performance of bulk silicon CMOS devices has gradually approached the physical limit of silicon materials, and further improving the performance of bulk silicon CMOS devices in the direction guided by Moore's law will face increasing investment and market risk. The semiconductor industry is a market that is very sensitive to the performance-price ratio of products. How to continuously improve the performance of silicon-based devices based on the existing VLSL process without increasing investment has become a common problem in the industry. The exploration of new materials and new processes is undoubtedly an important way of thinking and research direction to solve t...
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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
Inventor 张苗陈达狄增峰薛忠营叶林王刚母志强
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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