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A memory discharge circuit

A discharge circuit and memory technology, applied in static memory, digital memory information, information storage, etc., can solve the problem that the discharge speed of positive and negative voltages cannot be controlled

Active Publication Date: 2015-11-25
GIGADEVICE SEMICON SHANGHAI INC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved in this application is to provide a memory discharge circuit to solve the problem that the positive and negative voltage discharge speed cannot be controlled in the traditional discharge circuit

Method used

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Embodiment 1

[0040] In the first embodiment, a memory discharge circuit described in this application is introduced in detail.

[0041] refer to Figure 4 , shows a schematic diagram of a memory discharging circuit described in Embodiment 1 of the present application.

[0042] The memory discharge circuit described in this embodiment includes:

[0043] Internal voltage VDD; internal current source Idisc;

[0044] P tube current mirror composed of PMOS tube;

[0045] N-tube current mirror composed of NMOS tubes;

[0046] And, a negative voltage discharge branch and a positive voltage discharge branch;

[0047] Wherein, the P-tube current mirror includes a first PMOS transistor MP3 and a second PMOS transistor MP4, and three PMOS transistors MP0, MP1 and MP2;

[0048] The gate of the first PMOS transistor MP3 is connected to the internal current source Idisc, the source is connected to the internal voltage VDD, and the drain is connected to the negative voltage discharge branch for copy...

Embodiment 2

[0066] Embodiment 2 describes in detail a preferred solution of a storage discharge circuit described in this application.

[0067] refer to Figure 6 , which shows a schematic diagram of a preferred solution of a storage discharge circuit described in Embodiment 2 of the present application.

[0068] The memory discharge circuit described in this embodiment includes:

[0069] Internal voltage VDD; internal current source Idisc;

[0070] P tube current mirror composed of PMOS tube;

[0071] N-tube current mirror composed of NMOS tubes;

[0072] And, a negative voltage discharge branch and a positive voltage discharge branch;

[0073] Wherein, preferably, the P-tube current mirror includes a first PMOS transistor MP3 and a second PMOS transistor MP4, and three PMOS transistors MP0, MP1 and MP2;

[0074] The gate of the first PMOS transistor MP3 is connected to the internal current source Idisc, the source is connected to the internal voltage VDD, and the drain is connected...

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Abstract

The invention provides a discharging circuit of a memory to overcome the problem of uncontrollable discharging speeds of positive voltage and negative voltage in a traditional discharging circuit. The discharging circuit provided by the invention comprises a P-tube current mirror composed of PMOS tubes, an N-tube current mirror composed of NMOS tubes, a negative voltage discharging branch and a positive voltage discharging branch. Through controlling the number of the PMOS tubes in the circuit, the sizes of positive and negative voltage discharging currents are controlled, and the speeds of positive and negative voltage discharging currents are made to be identical in a same period of time. The speed of discharging current is controlled in the whole discharging process, so influence of an overfast discharging speed on the life of the memory is mitigated, and performance degradation of the memory is delayed; discharging in different periods of time is realized through adjusting the state of closing or opening of a switch, so discharging smoothness is improved.

Description

technical field [0001] The present application relates to the technical field of memory discharge, in particular to a memory discharge circuit. Background technique [0002] In the existing memory, the erase operation is a necessary step for writing data in the memory cell, which needs to apply a negative voltage (VNEG) to the gate (gate) of the memory cell and a positive voltage (VPW) to the well (well). Both voltages are typically generated by charge pumps. After erasing, the gate voltage and the well voltage must be discharged to GND (Ground, representing ground or 0). Discharging too fast can have a negative impact on the lifetime of the memory. [0003] Traditional discharge circuits such as figure 1 As shown, the negative voltage on the gate of the storage unit and the positive voltage on the well can be equivalent to a capacitor C0, and there is a switch tube DISP and DISN at both ends of the capacitor C0, and the discharge circuit discharges the two ends of the ca...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/12
Inventor 刘铭
Owner GIGADEVICE SEMICON SHANGHAI INC