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Method and device for reading nand flash memory

A memory array and flash technology, applied in read-only memory, static memory, information storage, etc., can solve problems such as read flow loss

Active Publication Date: 2016-06-15
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This delay is due to the significant loss of read throughput due to on-chip ECC

Method used

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  • Method and device for reading nand flash memory
  • Method and device for reading nand flash memory
  • Method and device for reading nand flash memory

Examples

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Embodiment Construction

[0020] Page buffers for NAND memory arrays are properly composed and operated to eliminate gaps and discontinuities in output data during successive page reads following an initial page read. The page buffer contains data registers for receiving page data transferred from the NAND memory array, and cache registers for receiving page data transferred from the data register, which in turn releases data registers to receive subsequent pages of data from the NAND memory array without causing any gaps or discontinuities in the data output from the cache registers. As used herein, the term "transfer" refers to the transfer of data from a source to a destination, and does not involve placing data at the source where it may remain undisturbed, deleted, refreshed, rewritten, modified, or otherwise processed. The cache register can be composed of two or more parts, and the page data in the cache register can be alternately and continuously output from the cache memory part. In a two-pa...

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Abstract

The invention discloses a method and device for reading NAND flash memory, the method includes: storing NAND memory array data in a data register, the page buffer has a data register and a cache register, the data register and a cache The fetch register is properly composed and operated to eliminate gaps and discontinuities in output data during consecutive page reads. The cache register can be composed of two parts, and the page data in the cache memory can be alternately output from the cache memory part. ECC delays can be removed from output by performing ECC calculations on one cache portion while another cache portion is being output. The data registers may also be composed of two sections corresponding to the cache sections, so that data may be transferred to the other cache section while being output from one cache section. In a variation, sequential page reads can be done without ECC.

Description

technical field [0001] The present invention relates to flash memory, and more particularly to methods and apparatus for reading NAND flash memory. Background technique [0002] NAND flash memory has become increasingly popular due to its significant cost advantages. One indicator of the cost of flash memory is the memory cell area, where the memory cell area is usually expressed in F*2. F is usually called the feature size (featuresize), which is usually the process generation. In other words, for the 58nm process generation, F is 58nm, and for the 46nm process generation, F is 46nm. The 4F*2 NAND flash memory cell size is significantly smaller than other competing technologies, such as NOR flash memory, whose cell size is in the range of about 12F*2 to 15F*2. [0003] Another well-developed part of flash memory is the Serial Peripheral Interface ("SPI") part. One reason for the popularity of serial NOR flash with SPI is the low pin count (eg, pins / CS, CLK, DI, DO for s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06G11C16/26
Inventor 安尼尔·古普特欧龙·麦可罗宾·约翰·吉高尔
Owner WINBOND ELECTRONICS CORP