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Stacked package device and manufacturing method thereof

A technology for packaging devices and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems such as high cost, limited number of stacked layers, and difficult expansion, so as to reduce difficulty and reduce overall thickness Effect

Active Publication Date: 2016-09-21
NAT CENT FOR ADVANCED PACKAGING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, multi-layer stacked packaging devices in the prior art are not easy to expand, and the number of stacked layers is limited. If it is necessary to increase the number of stacked layers, it is necessary to modify the design of the packaging components of all other layers, and it is also necessary to modify the entire stacked device. Large-scale adjustment of the production line and process, the cost is high

Method used

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  • Stacked package device and manufacturing method thereof
  • Stacked package device and manufacturing method thereof
  • Stacked package device and manufacturing method thereof

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Embodiment Construction

[0022] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0023] The detailed description of the present invention directly or indirectly simulates the operation of the technical solution of the present invention mainly through programs, steps, logic blocks, processes or other symbolic descriptions. In the ensuing description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. Rather, the invention may be practiced without these specific details. These descriptions and representations herein are used by those skilled in the art to effectively convey the substance of their work to others skilled in the art. In other words, for the purpose of avoiding obscuring the present invention, well-known methods and procedures have not been described in detail since they have been readily understood.

[0024] Reference herein to "one embodiment" or "an embodiment" refers to ...

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Abstract

The invention discloses a stacked packaging device. The stacked packaging device comprises a plurality of packaging assemblies which are installed together in a stacked mode. Each packaging assembly comprises a substrate provided with a first surface and a second surface, a groove formed in the first surface of the substrate, a semiconductor chip arranged in the groove, and an inner sealing material allowing the semiconductor chip to be sealed into the groove, wherein the upper surface of the semiconductor chip is lower than the first surface of the substrate, and the upper surface of the inner sealing material is basically flush with the first surface of the substrate. Each packing assembly further comprises a plurality of connecting parts which are connected to the second surface of the corresponding substrate. When every two adjacent packaging assemblies are installed in a stacked mode, the connecting parts of the upper packaging assembly are electrically connected to the first surface of the substrate of the lower packaging assembly. Therefore, the upper surface of each packaging assembly is of a full-flat structure, and the difficulty of the later stacked packaging is lowered, and more ways are provided for the subsequent stacked packaging.

Description

technical field [0001] The present invention relates to the field of semiconductor packaging, in particular to a multilayer package on package (Package on package, POP for short) device and a manufacturing method thereof. Background technique [0002] As the size of electronic devices decreases, high integration density can be achieved by stacking a plurality of chips in one semiconductor package or stacking a plurality of individual semiconductor packages. Recently, stacked semiconductor packages have been introduced for mobile electronic device applications and the like. One of the stacked semiconductor packages is a package-on-package (POP) in which a logic package device and a memory package device are stacked. Using the POP technology, different types of semiconductor chips can be included in one semiconductor package. [0003] However, the multi-layer stacked packaging devices in the prior art are not easy to expand, and the number of stacked layers is limited. If th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L23/31H01L23/13H01L21/50
CPCH01L24/73H01L2224/16225H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73265H01L2924/15153H01L2924/15311H01L2924/15331H01L2924/00012H01L2924/00H01L2924/00014
Inventor 张博尹雯陆原
Owner NAT CENT FOR ADVANCED PACKAGING CO LTD
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