Method for controlling parallelism degree of program capable of sensing band width of storage device

A storage device and control method technology, applied in multi-programming devices, concurrent instruction execution, machine execution devices, etc., can solve problems such as overall performance not increasing but decreasing, unable to maximize the advantages of parallel processing, and difficult to parallelize.

Inactive Publication Date: 2014-03-26
凯习(北京)信息科技有限公司
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Problems solved by technology

When applications that frequently access I/O devices run on different parallel platforms, it is difficult to directly determine the degree of parallelism that can maximize I/O efficiency. Too low parallelism will lead to insufficient utilization of I/O bandwidth and waste of processors Core resources; Excessively high parallelism may not necessarily improve performance. Since I/O bandwidth has become a bottleneck, excessively high parallelism will lead

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  • Method for controlling parallelism degree of program capable of sensing band width of storage device
  • Method for controlling parallelism degree of program capable of sensing band width of storage device
  • Method for controlling parallelism degree of program capable of sensing band width of storage device

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Embodiment Construction

[0073] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0074] see figure 1 As shown, the program running on the application platform can be divided into three states according to the I / O efficiency of the program, that is, the initial state, the steady state and the final state.

[0075] The initial state refers to a state when the application starts running with a lower degree of parallelism.

[0076] Steady state refers to a state when the application enters a stable operation after the initial state.

[0077] The final state refers to a state in which the application maintains a high I / O efficiency after going through a steady state.

[0078] The conversion mode between the initial state and the steady state is recorded as fast positioning, and the fast positioning refers to the process of increasing the parallelism according to the law of the exponential power of 2.

[0079] The conversion mode between the...

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Abstract

The invention discloses a method for controlling the parallelism degree of a program capable of sensing the band width of a storage device. By means of the method, the parallelism degree of the application program is dynamically adjusted according to the comprehensive performance and real-time loading conditions of the storage device of an operating platform of the application program in a self-adaptive mode, namely the number of courses or threads, so that the application program keeps and obtains the parallelism degree with the optimal I/O efficiency. According to the method, the information of the I/O efficiency of the application program is monitored and recorded in real time and is used as feedback information to control and adjust the parallelism degree of the application program. The parallelism degree of the program is probed step by step and increased gradually until the parallelism degree reaches the inflection point of the actual I/O efficiency, and then fine adjustment is carried out to obtain the optimal parallelism degree for different application program platforms; further according to the real-time loading conditions of the different application program platforms, periodic, dynamic and self-adaptive operation combining active adjustment and passive adjustment is carried out to obtain the optimal parallelism degree of the application program.

Description

technical field [0001] The invention relates to the control of the degree of parallelism of a parallel program suitable for on-chip multi-core multiprocessors, in particular to a method for controlling the degree of parallelism of a program that can sense the I / O bandwidth of a storage device. Background technique [0002] On-chip multi-core multi-processor (Chip Mulit-Processor, CMP) is to integrate multiple computing cores in one processor chip to improve computing power. The programs executed by each CPU core of the CMP processor need to share and synchronize data, so its hardware structure must support inter-core communication. [0003] After the emergence of CMP processing technology, the parallelization of traditional serial programs has become the focus of research. Most parallel programs use the number of CMP cores as an important reference index for selecting the degree of parallelism (number of processes or threads). Intensive applications have achieved better res...

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Application Information

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IPC IPC(8): G06F9/38G06F9/46
Inventor 刘轶王庆全刘弢李钦高飞朱延超
Owner 凯习(北京)信息科技有限公司
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