Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Graph optimization method for short-circuit path in integrated circuit layout verification

A technology of integrated circuits and graphics, used in electrical digital data processing, special data processing applications, instruments, etc.

Inactive Publication Date: 2014-03-26
北京华大九天科技股份有限公司
View PDF3 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Aiming at the short-circuit path positioning problem faced in integrated circuit layout design, the present invention proposes a short-circuit path graphic optimization method in combination with graphic segmentation and shortest path search methods

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Graph optimization method for short-circuit path in integrated circuit layout verification
  • Graph optimization method for short-circuit path in integrated circuit layout verification
  • Graph optimization method for short-circuit path in integrated circuit layout verification

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] The processing flow of this method is as follows Figure 1 Show. Introduce the concrete implementation of this method below in conjunction with example, as figure 2( As shown in a), potential S and potential D are short-circuited by connecting graph 1 and graph 2, but graph 1 and graph 2 cannot visually represent the connection of the short-circuit path, especially when there are many and complex graphs on the short-circuit path , it is difficult to intuitively represent the connection relationship of the short-circuit path. The optimized results of this method are as follows figure 2( As shown in b), by optimizing the graphics on the short-circuit path, the representation of the short-circuit path is more intuitive and concise. The following combination Figure 2 The example shown introduces the specific steps of this method:

[0020] Step 1: Use the scanning line method to segment the graphics. The segmentation of graph 1 is as follows image 3( As shown in a)...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a graph optimization method for a short-circuit path in integrated circuit layout verification, which belongs to the technical field of integrated circuit computer-aided design, and particularly relates to the field of design rule checking (DRC) and layout versus schematic checking (LVS) for an integrated circuit layout. The graph optimization method disclosed by the invention refers to the following three key steps: step one, splitting graphs, specifically, splitting complex graphs into simple trapezoids or triangles by means of a scanning line method; step two, abstracting a problem to a path finding problem for an undirected graph, finding a path with the fewest graphs from a source point to an end point by virtue of breadth-first traversal; and step three, combining the trapezoids or triangles obtained by splitting the same graph by virtue of the characteristics of the split graphs. The presentation of the short-circuit path in a layout can be effectively optimized to be more intuitive and simpler by utilizing the method in the integrated circuit layout verification, thus facilitating design personnel to rapidly locate a short-circuit position.

Description

technical field [0001] The invention relates to a graphic optimization method for short-circuit paths in an integrated circuit layout verification tool, and belongs to the technical field of computer-aided design of integrated circuits, and in particular relates to design rule checking (DRC) and layout and schematic diagrams of integrated circuit layouts The Consistency Check (LVS) field. Background technique [0002] With the development of integrated circuit technology, the feature size of the chip is getting smaller and smaller, the integration level of a single chip is constantly improving, the structure and process are becoming more and more complex, and the scale of the layout database is increasing exponentially. With the expansion of chip scale, the design rules that need to be verified in each stage of integrated circuit design are also increasing. Among them, the design rule check (DRC) of the integrated circuit layout and the consistency check (LVS) between the i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 丁丰庆王国庆王志明刘艳霞
Owner 北京华大九天科技股份有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com