Forming method of self-aligned double pattern

Abstract

The invention relates to a forming method of a self-aligned double pattern. The provided forming method comprises the following steps that: a to-be-etched layer is provided, wherein first sacrificial layers are arranged at the surface of the to-be-etched layer and the width of one first sacrificial layer is identical with the distance between the two adjacent first sacrificial layers; first mask side walls are formed at the surface of the to-be-etched layer at the two sides of the first sacrificial layers; second sacrificial layers covering the surfaces of the first mask side walls are formed at the surface of the to-be-etched layer, wherein the surfaces of the second sacrificial layers are flush with the surfaces of the first sacrificial layer; after the forming of the second sacrificial layers, the first sacrificial layers are removed and the surface of the to-be-etched layer is exposed; after removing of the first sacrificial layers, second mask side walls are formed at the second sacrificial layers and the etched layer surface at the two sides of the first mask side walls, wherein the profile shapes of the second mask side walls are symmetrical with those of the first mask side walls; and after the forming of the second mask side walls, the second sacrificial layers are removed. According to the invention, the pattern that is formed by using the formed double pattern as the mask for etching has the unified dimension and morphology.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a self-aligned double pattern. Background technique [0002] With the continuous progress of semiconductor technology, the process nodes of semiconductor devices are continuously reduced. However, due to the limitation of the precision of the existing photolithography process, the mask pattern formed by the existing photolithography process is difficult to meet the demand for continuous reduction of the feature size of semiconductor devices, which hinders the development of semiconductor technology. [0003] In order to further reduce the size of the semiconductor device on the basis of the existing photolithography process, a double patterning process is proposed in the prior art. Among them, the self-aligned double patterning (Self-Aligned Double Patterning, SADP) process is widely used because of its simplicity. Figure 1 to Figure 5 I...

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Problems solved by technology

[0009] However, in the prior art, after etching with a mask formed by a self-aligned double patterning process, the pattern formed by etching has poor morphology and is difficult to control in size

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