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Semiconductor device manufacturing method

A device manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as poor process controllability and achieve good controllability

Active Publication Date: 2018-02-13
SOI MICRO CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The invention provides a method for manufacturing a transistor, which uses spacer technology to form a gate similar to the gate last process (gatelast), which overcomes the defect of poor process controllability in the prior art

Method used

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  • Semiconductor device manufacturing method
  • Semiconductor device manufacturing method
  • Semiconductor device manufacturing method

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Embodiment Construction

[0029] Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

[0030] The present invention provides a method for manufacturing a semiconductor device, and in particular relates to a method for manufacturing a transistor using spacer technology. Please refer to the attached Figure 1-16 , the semiconductor device manufacturing method provided by the present invention will be described in detail.

[0031] First, see attached figure 1 , forming a patterned first material layer 2 on the semiconductor substrate 1 . Specifically, a semiconductor substrate 1 is provided. In this embodiment, a single crystal silicon substr...

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Abstract

The invention provides a transistor manufacturing method utilizing a gap wall technology to form a gate electrode. In the transistor manufacturing method, the first gap wall, the second gap wall, the third gap wall and the fourth gap wall are sequentially formed, a gate electrode groove with the width controlled by the second gap wall is formed by removing the second gap wall, and then the required gate electrode and a gate electrode insulating layer are formed in the gate electrode groove. In the method, the gap walls are formed through back etching without an additional mask. In addition, the gate electrode width is defined by controlling the width of the second gap wall, formation of a 45nm sub gate electrode line can be achieved, and a process has good controllability.

Description

technical field [0001] The invention relates to the field of manufacturing methods of semiconductor devices, in particular to a method for manufacturing transistor devices using spacer technology to form gates. Background technique [0002] After semiconductor integrated circuit technology enters the technology node of 90nm feature size, it becomes more and more challenging to maintain or improve transistor performance. In the sub-45nm area, high-K gate insulating materials and metal gates are used to maintain and improve transistor performance. However, when the size of the gate line enters the sub-45nm field, the controllability of the gate line formation process begins to encounter great difficulties. People cannot well control the shape of the obtained gate line, which will affect the Transistor performance. [0003] Therefore, it is necessary to provide a new method for manufacturing transistors, which can form sufficiently fine gate lines while making the process con...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/336
CPCH01L21/28132H01L21/28141H01L29/6656H01L29/66568H01L29/78
Inventor 秦长亮梁擎擎殷华湘毛淑娟
Owner SOI MICRO CO LTD