A system for realizing tap device function based on fpga

Abstract

The invention discloses a system for realizing the functions of TAP equipment based on FPGA, which realizes one-to-one or one-to-many replication through a fast path module, directly passes through from an input port to an output port, and realizes fast data copying and forwarding; the internal cache module is embedded The RAM is divided into multi-level implementations, and the read-write control of each level is different, which ensures that the full flow does not cause packet loss when transmitting random packets; In its rate mode, the port data on the network side is scheduled and forwarded through itself, so as to realize data aggregation and load balancing functions, solve the problems of resource competition and insufficient bandwidth, and increase the utilization rate of channel bandwidth.

Description

technical field [0001] The invention relates to the field of network equipment, in particular to a system for realizing the functions of TAP equipment based on FPGA. Background technique [0002] Ethernet tap (TAP device) is a kind of Ethernet traffic replication device, which can obtain network data in real time without interrupting normal network traffic, and accurately monitor bidirectional sessions at full wire speed. Therefore, TAP equipment is an indispensable solution for obtaining IP traffic and content information in operators' network traffic analysis and value-added service systems, mobile network signaling monitoring and content monitoring systems, IDC content audit detection, IP network security, IP intrusion detection, IP content audit and other solutions. missing equipment. [0003] Traditional Ethernet splitters (TAP devices) generally have three implementation methods, one is to use Ethernet PHY chips for back-to-back connection; the other is to implement t...

AI Technical Summary

Problems solved by technology

It can be found that the data can only be replicated one-to-one, and cannot be replicated one-to-many or aggregated many-to-one; PHY1, PHY2, PHY3, and PHY4 must maintain the same working rate, otherwise the monitoring side link will fail The data is collected, and the function is relatively simple

[0005] refer to figure 2 The TAP device implemented with an embedded switch chip is limited by the data storage and forwarding mechanism of SWITCH. Generally, the data packet stays in SWITCH for a long time and is not fixed, resulting in a large forwarding delay (microsecond level). In particular, network-side ports that are more sensitive to delay have the most serious impact; limited by the functional limitations of SWITCH, most low-end and mid-range SWITCHs cannot achieve port-based traffic balancing in terms of load balancing functions; limited by the functional limitations of SWITCH, SWITCH will discard some MAC control frames and error packets, and cannot achieve 100% data capture at full wire speed, making the TAP device unable to present all network data

[0006] refer to image 3 The TAP device implemented by the NPU shown in the figure is limited by the soft processing mechanism of the NPU, and the forwarding delay is relatively large, and the processing of Ethernet data cannot be done in real time, especially the delay-sensitive network-side ports are most seriously affected; the NPU needs There are many peripheral configuration circuits in the system, which increases the complexity and cost of the system; due to the limitation of the NPU soft processing speed and the efficiency of software algorithms, it is impossible to achieve real-time large-flow data processing

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