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Smart Context Management

A contextual, intelligent technology used in the field of computer systems to solve problems such as interruptions

Active Publication Date: 2017-06-27
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the thread then tries to use one of these devices, an interrupt will result and the operating system can then restore the desired state and enable access to the requested device

Method used

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Embodiment Construction

[0016] Although hardware multithreading has greatly increased the processing throughput of modern microprocessors, there are still a number of limitations associated with the different approaches to thread switching. Lazy context management works when a thread only occasionally or intermittently needs to access the FPR, VR, or VSR, thereby reducing normal context switch time. However, if a thread continues to use one of these devices, there is an added delay after each context switch due to the constant interruption required to restore the state.

[0017] This problem is magnified in state-of-the-art systems by the recent addition of transactional memory. Transactional memory is a way to ensure atomicity, allowing speculative concurrent access to shared memory. It replaces the practice of locking data until complex work is done, a way to slow down other computer operations. Transactional memory attempts to simplify concurrent or parallel programming by allowing a set of load...

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Abstract

Intelligent context management for thread switching is achieved by determining that a register bank is not used by a thread for a predetermined number of dispatches and responsively disabling the register bank from use by that thread. Increment the counter every time a thread is dispatched but the register bank is not in use. The use or non-use of a register bank is inferred by comparing the previous checksum and the current checksum for the register bank. If the previous checksum and the current checksum match, the system concludes that the register bank is not in use. If a thread attempts to access a disabled bank, the processor is interrupted and the corresponding counter is reset. For systems utilizing transactional memory, it is preferable to enable all register banks at the start of thread processing to avoid aborted transactions from register banks disabled by the slack context management technique.

Description

technical field [0001] The present invention relates generally to computer systems, and more particularly to a method of managing thread contexts in a multithreaded processor. Background technique [0002] Today's high-performance computer systems use multiple processors to execute various computer programs, such as software applications and operating systems. In a symmetric multiprocessor (SMP) computer, all processing units are typically identical, ie, they all operate using a common set or subset of instructions and protocols, and typically have the same architecture. Each processing unit may further include a plurality of processor cores that actually execute the program instructions to operate the computer. Processor cores can operate according to Reduced Instruction Set Computing (RISC) technology, and can use pipelining and out-of-order execution of instructions to further improve the performance of superscalar architectures. [0003] In a superscalar architecture, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/48G06F9/38
CPCG06F9/461G06F9/30123G06F9/3834G06F9/3851G06F9/38585G06F9/3888
Inventor R·C·斯旺贝格
Owner INT BUSINESS MASCH CORP