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Multi-phase clock generation circuit

A multi-phase clock and generation circuit technology, applied in electrical components, signal generation/distribution, static memory, etc., can solve the problem of time input/output data, cannot generate normal operation of semiconductor memory devices, and cannot fully guarantee the high speed of semiconductor memory devices. Operation margin and other issues to achieve the effect of ensuring sufficient margin

Active Publication Date: 2014-06-11
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for an internal clock generated using a D flip-flop, a margin required for high-speed operation of a semiconductor memory device cannot be sufficiently secured due to an internal time delay propagated through the D flip-flop and the inverter.
Therefore, since data cannot be input / output at the correct timing, normal operation of the semiconductor memory device cannot be produced

Method used

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Examples

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Embodiment Construction

[0016] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the examples are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0017] Such as figure 1 As shown, the multi-phase clock generation circuit according to an embodiment of the present invention may include a first clock buffer unit 1 and a second clock buffer unit 2 . The first clock buffer unit 1 may be configured to buffer the first and second internal clocks ICLKRA and ICLKRB in response to the external clock CLK and the inverted external clock CLKB, and to generate third and fourth internal clocks ICLKFA and ICLKFB. The second clock buffer unit 2 may be configured to buffer the third and fourth internal clocks ICLKFA and ICLKFB in response to the external clock CLK and the inverted external clock CLKB, and to generate the first and second internal clocks ICLKRA and ICLKRB.

[0018] The first cloc...

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Abstract

A multi-phase clock generation circuit includes a first clock buffer unit and a second clock buffer unit, wherein the first clock buffer unit is configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock; and the second clock buffer unit is configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2012-0137370 filed on November 29, 2012, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to the technical field of semiconductors, and more specifically, to a multi-phase clock generation circuit. Background technique [0004] In recent years, in order to realize high-speed operation of semiconductor memory devices, a plurality of internal clocks having a plurality of phases for inputting / outputting data are used. For example, instead of inputting / outputting data based on one external clock, a method has been proposed in which four internal clocks having a phase difference of 90° from each other are generated and used for data input / output to realize High speed operation. [0005] Multi-phase internal clocks can be generated using multiple D flip-flops. To generate two inte...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/40H03K5/135
CPCH03K5/15066G06F1/06H03K5/15
Inventor 李相权
Owner SK HYNIX INC