non-volatile semiconductor storage device

Abstract

The invention discloses a non-volatile semiconductor storage device, which can more flexibly set the voltage for accumulating charge in a selected memory cell transistor compared with the conventional device. In the non-volatile semiconductor storage device (1), when accumulating charge in the selected memory cell transistor (115), a high voltage is applied from the P-type MOS transistor (9b) as a write-in blocking voltage, and the N-type MOS transistor ( 15a) Applying a low voltage as a write voltage, the task of applying a voltage to the selected memory cell transistor (115) or the unselected memory cell transistor (116) is performed by the P-type MOS transistor (9b) and the N-type MOS transistor (15a ), thus, the respective gate voltage and source voltage of the P-type MOS transistor (9b) and the N-type MOS transistor (15a) can be adjusted respectively, and the gate-to-substrate voltage can be finally set to, for example, 4 [V] Wait.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor storage device. Background technique [0002] At present, a typical nonvolatile semiconductor memory device, such as a type of nonvolatile semiconductor memory device, has been well known, and this type of semiconductor memory device, for example, through the quantum tunneling effect, to the charge accumulation layer of the memory cell transistor Charges are internally accumulated so that a data writing process is performed (for example, refer to Patent Document 1). In fact, if Figure 6 As shown, this type of nonvolatile semiconductor memory device 100 has a structure in which high-order bit lines 101a, 101b and word lines 102a-102h are arranged in a crossing manner, and a plurality of memory cell transistors 103 are arranged in relation to the high-order bit lines. In the rows and columns of the matrix of lines 101a, 101b and word lines 102a-102h. [0003] A plurality of first semiconduct...

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Problems solved by technology

[0023] However, the nonvolatile semiconductor memory device 100 having such a structure has the following defect: when the write prevention voltage from the unselected bit line 123 is applied to the unselected memory cell transistor 116 on the selected word line 120, due to the second One semiconductor switch 104b is constituted by an N-type MOS transistor. In order to turn on the first semiconductor switch 104b, it is necessary to apply a writing prevention voltage higher than 8[V], about 10[V], from the unselected bit line 123. V] gate voltage, then the problem of excessive voltage inevitably occurs

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