3D memory structure and operating method of 3D memory structure

Abstract

The invention discloses a 3D memory structure and an operating method of the 3D memory structure. The3D memory structure comprises multiple stacked structures, multiple charge trapping multilayers, multiple ultra-thin channels and a dielectric layer, wherein the multiple stacked structures are formed on a substrate and are perpendicular to the substrate, the charge trapping multilayers are located on the peripheries of the multiple stacked structures, and the dielectric layer is arranged outside the ultra-thin channels and located between the stacked structures. Each stacked structure comprises bottom gates which are connected, multiple gates, multiple gate insulators are arranged on the bottom gates in a staggered and stacked mode, and two selection lines arranged above the gates in a spaced mode and are controlled independently, the multiple selection lines are insulated from one another through the corresponding gate insulators, the selection lines are insulated from the gates through the corresponding gate insulators, and the tops of the selection lines are insulated from one another through the corresponding insulators; the ultra-thin channels are located outside the charge trapping multilayers and are lined between the stacked structures, and a U-shaped channel is formed by every two ultra-thin channels formed in the opposite side faces of every two adjacent stacked structures. A word line selector area which comprises multiple ultra-thin U-shaped channels and a pair of word line selectors is formed between every two adjacent stacked structures, and the word line selectors are located on the two sides of the ultra-thin U-shaped channels and used for controlling the multiple ultra-thin U-shaped channels.

Description

technical field [0001] Embodiments of the present invention relate to a three-dimensional memory structure and its operating method, and more particularly to a single-gate three-dimensional memory structure and its operating method. Background technique [0002] A great feature of non-volatile memory element design is the ability to preserve the integrity of the data state when the memory element loses or removes power. Currently, many different types of non-volatile memory devices have been proposed in the industry. However, related companies are still developing new designs or combining existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some stacked NAND gate (NAND) flash memory structures have been proposed. [0003] In some proposed three-dimensional memory structures, in addition to single-gate (Single-Gate) memory cells, it also includes double-gate (double gate) memory cells, and surrounding gat...

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Problems solved by technology

In addition, reducing the size of the memory cell is not only about considering the charge trapping layer, but also needs to consider the design rules of other components as a whole. The high complexity of the design of the double-gate and wrap-around gate memory cells also limits the size of the three-dimensional memory. The development of miniaturization, if it is to make it have both small size and good various electronic characteristics, its high degree of design difficulty will inevitably consume a lot of time and greatly increase the manufacturing cost

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