Direct-current offset calibration method and circuit for pipelined analog-to-digital converters

Abstract

The invention provides a direct-current offset calibration method and an implementation circuit thereof for pipelined analog-to-digital converters. The calibration method comprises the following main steps: step 1, analog inputs VIP and VIN of a pipelined analog-to-digital converter are connected with an input common-mode voltage VCM; step 2, digital output of a core circuit of the analog-to-digital converter is sampled every X clock cycles, sampling is repeated for Y times, and an average value is taken and written into a memory module, wherein X and Y are integers and values thereof can be selected as required by calibration time and calibration precision; step 3, the analog inputs VIP and VIN of the analog-to-digital converter are connected with an input signal, and the analog-to-digital converter enters a normal working state; and step 4, subtraction is performed between the direct-current offset average value written into the memory module and digital output of the core circuit in a normal working state to finally obtain digital output with direct-current offset calibration. Direct-current offset of pipelined analog-to-digital converters can be reduced, and the dynamic range of analog-to-digital converters is increased.

Description

technical field [0001] The invention proposes a DC offset calibration method and a realization circuit for an analog-to-digital converter with pipeline structure. Background technique [0002] See figure 1 and figure 2 As shown, it is an existing common pipeline analog-to-digital converter stage circuit, each stage is 1.5 bits, controlled by two-phase non-overlapping clocks, and works alternately in the sampling phase and the holding phase. Among them, C1 and C2 are sampling capacitors with equal capacitance values, 110 is an operational amplifier, VIN is the input voltage of the stage circuit, VOUT is the output voltage of the stage circuit, b=-1 or 0 or +1, and VREF is the value of the stage circuit for subtraction reference voltage. Ideally, at the end of the sampling phase, the total charge stored on capacitors C1 and C2 is Q1=VIN*C1+VIN*C2=2*VIN*C1; at the end of the hold phase, the total charge stored on capacitors C1 and C2 Q2=b*VREF*C2+VOUT*C1=(VOUT+b*VREF)*C1. ...

AI Technical Summary

Problems solved by technology

The existing method to eliminate the DC offset of the operational amplifier in the pipeline stage circuit is often to improve the timing or circuit structure of the analog circuit in the stage circuit. Although it can reduce the DC offset, it will increase the complexity of the circuit and introduce new parasitics, thereby affecting the accuracy and speed of the ADC to some extent

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