Test Structure and Its Layout Generation Method

Abstract

The present invention provides a test structure, including a substrate and n×m arrays of sub-MOS structures on the substrate, each sub-MOS structure includes a gate and an active region; row i, row j The sub-MOS structure of the column also includes a gate through hole and an active region through hole; n≥3, m≥3, 1<i<n, 1<j<m, n, m, i, j are all positive integer. The invention also provides a layout generation method of the test structure. In the test structure, the sub-MOS structures in row i and column j are used as MOS transistors to be tested, and the rest of the sub-MOS structures are used as redundant MOS transistors to improve the pattern density distribution in the test structure The uniform type makes the test structure avoid being greatly affected by processes such as chemical mechanical grinding and etching during the preparation process, thereby improving the accuracy of reliability test results.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a test structure and a layout generation method thereof. Background technique [0002] As the feature size of CMOS semiconductor manufacturing technology shrinks, in order to meet the requirements of function and high yield, it is necessary to monitor the process for process fluctuations. At present, the most commonly used method is electrical testing in time, therefore, it is necessary to prepare a special test structure for process monitoring. [0003] In the prior art, the pattern density distribution in the test structure of the MOS tube is not uniform, so that the test structure of the MOS tube is greatly affected by processes such as chemical mechanical grinding and etching during the preparation process, thus making the electrical test The result is inaccurate; moreover, each pattern (patten) in the layout of the existing test structure is manually drawn by the lay...

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Problems solved by technology

[0003] In the prior art, the pattern density distribution in the test structure of the MOS tube is not uniform, so that the test structure of the MOS tube is greatly affected by processes such as chemical mechanical grinding and etching during the preparation process, so that the electrical test The result is inaccurate; and each pattern (patten) in the layout of the existing test structure is drawn manually by the layout designer, and there are differences in the shapes and sizes between the patterns, which further affect the results of the electrical test

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