Ldmos device with double-sloped field plate

Abstract

In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate.

Description

technical field [0001] This specification relates to laterally diffused metal oxide semiconductor transistors and methods of forming the same. Background technique [0002] Designing and engineering transistors for production using semiconductor processes typically involves trade-offs of one or more performance parameters with one or more other performance parameters. Such performance parameters may include drain-source on-resistance (Rdson), off-breakdown voltage (BVoff), and on-breakdown voltage (BVon), as some examples. For example, in laterally diffused metal-oxide-semiconductor (LDMOS) transistors, the dopant dose in the drift region (drift dose or DD) can be altered to vary the Rdson of a given LDMOS transistor. For example, increasing the drift dose of the semiconductor process used to produce a given LDMOS transistor will reduce the Rdson of that transistor compared to an LDMOS transistor of the same physical configuration produced using a lower drift dose. [0003...

AI Technical Summary

Problems solved by technology

As performance requirements for semiconductor devices increase, producing transistors with acceptable Rdson values ​​and acceptable breakdown voltage values ​​may not be achievable using current methods

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