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Low clock energy double-edge trigger flip-flop circuit

A dual-edge trigger and flip-flop technology, applied in logic circuits, electrical components, and generating electrical pulses, can solve problems such as power consumption

Active Publication Date: 2017-11-17
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Most of the power dissipated in conventional digital integrated circuits is dissipated in the clock network

Method used

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  • Low clock energy double-edge trigger flip-flop circuit
  • Low clock energy double-edge trigger flip-flop circuit
  • Low clock energy double-edge trigger flip-flop circuit

Examples

Experimental program
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Embodiment Construction

[0022] Reducing the number of loads on the clock signal provided as input to the flip-flop circuit reduces the energy consumed by the clock signal. The flip-flop circuit can be configured as a dual-edge triggered flip-flop that takes the state of input D on both edges of the clock signal to update output Q. When the input D is stable, the power consumed by the flip-flop circuit triggered by both edges is reduced because the internal nodes are not switching. Compared to a conventional single-edge triggered flip-flop circuit, which typically has 12 loads (ie, transistor gates) to the clock signal, a dual-edge triggered flip-flop circuit has 4 loads to the clock signal. Because a dual-edge-triggered flip-flop operates at twice the frequency of a conventional single-edge-triggered flip-flop circuit, a dual-edge-triggered flip-flop provides 6x reduction in clock energy. In an embodiment in which the keeper transistor is omitted, the dual-edge-triggered flip-flop circuit has only ...

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Abstract

Low clock energy double edge triggered flip-flop circuit. A dual-edge-triggered flip-flop circuit and a method for operating a dual-edge-triggered flip-flop circuit are provided. A subcircuit of the flip-flop circuit is coupled to ground and decouples the subcircuit from the power supply when the clock signal is asserted. The subcircuit generates trigger signals including a first pair of signals and a second pair of signals. The first pair of signals is evaluated when the clock signal is asserted, the levels of the second pair of signals are asserted, and the output signal transitions based on the trigger signal to equal the input signal when the clock signal is asserted.

Description

technical field [0001] The present invention relates to circuits, and, more particularly, to flip-flop circuits. Background technique [0002] Conventional devices such as microprocessors and graphics processors used in high performance digital systems may have varying current requirements based on processing workload. Power loss is an important issue in conventional integrated circuits. Most of the power dissipated in conventional digital integrated circuits is consumed in clock networks. The amount of energy dissipated by the flip-flops due to data transitions is small because the activity factor, ie the time fraction of the flip-flop's data input switching, is rather low, typically around 5-10%. In contrast, clock input loading and clock energy are increasingly important metrics to consider when determining the energy dissipated by latches and flip-flops in conventional integrated circuits. Reducing the clock switch capacitance by a given amount yields a 10X power savi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/094
CPCH03K3/356121H03K3/012
Inventor 威廉·J·达利
Owner NVIDIA CORP