Static memory cell and forming method thereof

Abstract

A static memory cell and a forming method thereof are provided; the static memory cell comprises the following elements: a semiconductor substrate comprising a first zone forming a pull down transistor and a second zone forming a pull up transistor; a first pin portion positioned on a surface of the semiconductor substrate in the first zone and a second fin portion positioned on a surface of the semiconductor in the second zone, wherein a top of the second fin portion is provided with an insulation layer; an interlayer medium layer covering the semiconductor substrate surface besides the first fin portion and the second fin portion, and a surface of the interlayer medium layer is lower than a top surface of the first and second fin portions; a first grid electrode structure positioned on the surface of the interlayer medium layer and capable of crossing the top and a side wall of the single first fin portion, and a second grid electrode structure positioned on the surface of the interlayer medium layer and capable of crossing a top and a side wall of the single second fin portion, and the second grid electrode structure is isolated from the top portion of the second fin portion through an insulation layer. The static memory cell is stable in performance, and a finally formed SRAM memory is excellent in performance.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a static storage unit and a method for forming the same. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in computers, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] figure 1 It is a schematic diagram of the circuit structure of the storage unit of the existing 6T structure SRAM memory, the storage unit includes: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3 and a fourth NMOS transistor N4. [0004] The first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2...

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Problems solved by technology

[0008] However, as the process node is further reduced, the performance of the SRAM memory formed by the prior art is not stable enough

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